I'm digging into left and right shift operations in ASM.
From IA-32 Intel Architecture Software Developer’s Manual 3
All IA-32 processors (starting with the Intel 286 processor) do mask the shift count to 5 bits, resulting in a maximum count of 31. This masking is done in all operating modes (including the virtual-8086 mode) to reduce the maximum execution time of the instructions.
I'm trying to understand the reasoning behind this logic. Maybe it works as it works because on a hardware level it is hard to implement shift for all 32 (or 64) bits in a register using 1 cycle?
Any detailed explanation would help a lot!