The CD4013B datasheet by TI contains the following statement:

Setting or resetting is independent of the clock and is accomplished by a high level on the set or reset line, respectively.

Table 1. Function Table in the datasheet matches this statement.

The datasheet also contains the following Logic Diagram (the colored alterations are mine):

Logic Diagram from the datasheet

It seems to me that the datasheet contains at least one error and one contradiction:

(a) Inverter (A), or any one of the series inverters in the Q circuit, should not be there. As drawn, the Q output will be a copy of the Q̅ output.

(b) The transmission gate (B) makes sure the RESET input will only take effect when the CL input is low (or high? I've never seen TGs denoted with such symbols and not sure what exactly "p" and "n" mean here). This is in contradiction with the statement above and the Table 1. (Meanwhile the SET input does work independently of CL, according to the diagram).

Main question: are the (a) and (b) above correct? (or am I -crazy- missing something obvious)

Additional question: can I consider the diagram illustrative and just ignore it, assuming Table 1 is normative? Or should I consider the details of the RESET function unreliable and design around them? (assuming I'm stuck with this chip)

  • 1
    \$\begingroup\$ Yes, just consider the diagram illustrative. The function table and the descriptive text is what you need to go by. Keep in mind that IC vendors update their internal designs every so often, and so the illustration shown may or may not represent the current part. \$\endgroup\$ – SteveSh May 12 '20 at 16:54

This is the original logic diagram as drawn by Harris, from revision D (2005) of the TI datasheet:

Harris CD4013B logic diagram

There is indeed a wrong inverter.

A transmission gate is a closed switch when the positive control input is 1, and the negative, 0.

The RESET input goes both to the master section and, if CL is high, to the /Q output. When CL is low, a high RESET value makes the leftmost NAND gate output 1, which goes through the topmost transmission gate to /Q.

  • \$\begingroup\$ I'm curious. How do you know it was drawn by Harris? It seems a shame that many of these datasheets are now only available as poor scans of printed copies. The original files have been lost. \$\endgroup\$ – Transistor May 13 '20 at 15:28
  • \$\begingroup\$ The 4000 series of CMOS ICs was introduced by RCA in 1968. So I'm not sure the term "original logic diagram as drawn by Harris" is accurate. \$\endgroup\$ – SteveSh May 13 '20 at 16:39
  • \$\begingroup\$ @Transistor The Harris logic product line was bought by TI; this is from the previous revision of the same datasheet. \$\endgroup\$ – CL. May 14 '20 at 8:58
  • \$\begingroup\$ @CL: That rings a bell alright. I seem to remember it from the articles in Electronics Today International in the 1970s. (I originally thought that you meant that Harris was the draftsman of some fame!) \$\endgroup\$ – Transistor May 14 '20 at 9:13
  • \$\begingroup\$ Thank you @CL.! Turns out I was missing something obvious, namely the master section part of the RESET path. (does a facepalm) \$\endgroup\$ – atzz May 20 '20 at 12:16

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