I'm using the following logic in a design:
module flipflip (
input wire d,
input wire clk,
input wire en,
output reg q
);
always @(posedge clk) begin
if (en) begin
q <= d;
end
end
endmodule
However, the behavior I actually want is
module flipflip (
input wire d,
input wire clk,
input wire en,
output reg q
);
always @(posedge clk) begin
if (en) begin
q <= d;
end else begin
q <= q;
end
end
endmodule
That is, if the en
flag isn't asserted the flip flop should just keep it's old value. Are these necessarily equivalent? I.e. do I have to code the 2nd, or can I get away with coding the 1st?
I wasn't able to track this down in the Verilog 2005 standard. Where is this covered?