1
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I'm using the following logic in a design:

module flipflip (
   input wire d,
   input wire clk,
   input wire en,
   output reg q
);
always @(posedge clk) begin
   if (en) begin
      q <= d;
   end
end
endmodule

However, the behavior I actually want is

module flipflip (
   input wire d,
   input wire clk,
   input wire en,
   output reg q
);
always @(posedge clk) begin
   if (en) begin
      q <= d;
   end else begin
      q <= q;
   end
end
endmodule

That is, if the en flag isn't asserted the flip flop should just keep it's old value. Are these necessarily equivalent? I.e. do I have to code the 2nd, or can I get away with coding the 1st?

I wasn't able to track this down in the Verilog 2005 standard. Where is this covered?

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3 Answers 3

4
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Yes, they are equivalent. IEEE Std 1364-2005, section 6.2 Procedural assignments states:

...procedural assignments put values in variables. The assignment does not have duration; instead, the variable holds the value of the assignment until the next procedural assignment to that variable.

You do not need to use the 2nd code example.

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1
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The IEEE Std1800-2017 is the current LRM. Section 6.5 Nets and variables says:

Variables can be written by one or more procedural statements, including procedural continuous assignments. The last write determines the value.

So they are equivalent. But there is also a uniform synthesis coding guide that says something like

A storage device gets inferred whenever you write to a variable in some branches of an always block, but not all, and that variable is read without being written to, or referenced outside that block.

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0
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Your two examples are functionally equivalent - the first one is common practice

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2
  • \$\begingroup\$ Great, I thought so, I just wanted to be sure. Any chance you know where this is discussed in the standard? \$\endgroup\$
    – MattHusz
    May 12, 2020 at 22:57
  • 1
    \$\begingroup\$ @MattHusz: I added an Answer. \$\endgroup\$
    – toolic
    May 13, 2020 at 0:16

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