# Physical size of the registers for x86

We have an 8-bit register called CL on x86 CPU architecture.

Does it mean that physically it contain 32 bits, but we have access only to lower 8 bits? Or does this register physically have only 8 bits?

So in general my question is: Are all the registers physically have the same size (say 32 bits) or not?

Not really greatly researched, a quick search on x86 registers led me here, but yes:

The L in CL is for Lower, its the lower byte of the 16-bit counter register CX, which itself is the lower half of the 32-bit ECX register.

This logic applies to most registers in IA32 (not all).

Are all the registers physically have the same size (say 32 bits)

no.

• Thank you! This logic applies to most registers in IA32 (not all). Does it mean that some register could be let's say 16-bit and others 32-bits on the same CPU? May 13 '20 at 9:02
• strange question: CL is 8 bit, CX is 16 bit ECX 32 bit, all exist on the same intel 386. So yes? May 13 '20 at 9:03
• The reason behind my question the following: MOV CL, 1 ->CL = 0000 0001 at the same time it will affect other registers: CX - > 0000 0000 0000 0001, ECX - > 0000 0000 0000 0000 0000 0000 0000 0001 As you can see, CL, CX and ECX physically is just parts of one register. So it seems that physically they all are the same size. May 13 '20 at 9:06
• Yes? It looks like you've answered your own question. They're part of the same register. May 13 '20 at 9:08
• I linked to a site above, if you read it you'll find the segment pointer registers to be 16 bit only. Also, remember how your FPU (on anything since the 486DX) has instructions to do double-precsion calculations, on 64 bit words? These operate on 64 bit registers! May 13 '20 at 9:16

Back in the olden days, the 8088 and 8086 had four general-purpose registers, named AX, BX, CX, and DX. Those registers were all 16 bits wide. Each register could also be accessed as two 8-bit chunks, the high byte and the low byte. Those 8-bit chunks were AH/AL, BH/BL, CH/CL, and DH/DL. Assigning a value to AH changes the contents of the upper byte of the AX register; assigning a value to AL changes the contents of the lower byte of the AX register.

Then the 80386 came along. It used 32-bit wide registers, but preserved the 16-bit and 8-bit features of the 8086. That way, assembly programs written for the 8088/8086 could be re-assembled to target the 80386 without having to rewrite the code. The 32-bit registers were named EAX, EBX, ECX, and EDX. The lower 16 bits of each of those registers could be addressed by the old names, AX, BX, CX, and DX. The low 8 bits of each register could be addressed by their old names, AL, BL, CL, and DL. Further, the upper 8 bits of each of the lower (16-bit) registers could still be addressed by their old names, AH, BH, CH, and DH.

I'm sure you can guess what happened when Intel introduced 64-bit processors. Yup, all the old names were still there with the same meanings, but those 8-bit, 16-bit, and 32-bit registers were each part of a 64-bit general register. The names of the 64-bit registers are RAX, RBX, RCX, and RDX. RAX is 64 bits wide; EAX is the lower 32 bits of RAX; AX is the lower 16 bits of RAX; AL is the lower 8 bits of RAX; and AH is bits 9-16 of RAX.

That's the story of the general registers in the 8086 family. There are other registers with various specialized roles, and their sizes are appropriate for what they do. For example, on the 80386, as mentioned earlier, the general registers are 32 bits wide. The segment registers (which are used to calculate the physical address of the memory being accessed) are 16 bits wide. So, no, not all registers are the same size.

I'm a digital IC designer, but I have no knowledge on x86 CPUs.

I think CL/CX/ECX are just software terms which are used to refer to different portion of a hardware entity (let's name it 'REG'). The 'REG' with certain bit width is the real memory device (probably flip-flops) inside the CPU circuit which is addressible. Why is CL for narrower 'REG' introduced? Perhaps shorter instruction is generated, hence optimized machine code can be achieved. Or there're other reasons, I don't know. Different machine code for CL/CX/ECX can lead to assertion of different control signals after the decode block of CPU decodes it. Those control signals plus the address of the entire 'REG' allows you to access specific portion of 'REG'.