I started learning about latches and flip flops recently, and my understanding is that edge-triggered devices like flip flops ignore their inputs until the clock signal transitions from low to high or from high to low, depending. This timing diagram show the output of a falling edge D FF that I expected in a particular edge case


Indeed, I found this very result with the following master-slave D FF simulated in software

Master-slave falling edge D FF

Then I learned about the JK flip flop and, while I understand what it's supposed to do, I am confused about something.

Master-slave falling edge JK FF

With the circuit above I tried something similar to what I did with the D FF :


I expected Q not to change and stay low since J and K were not high when the clock transitioned from high to low.

This is why I am confused : to me, this contrasts with other edge-triggered flip flops like the D or T, which only change their output based on what the inputs were at the transition of the clock signal (whether rising, falling, or both). Here, the outputs of the JK FF only change at the falling edge, but even if the values of the inputs are the same at two consecutive falling edges, if they have changed in between then the output will reflect it. As I had understood, this is not what an edge-triggered devise should do. I believe it is due to the fact that this JK FF is realy two SR latches in series. So as long as the clock is high, the master latch can capture the inputs but does not need them to be held until the clock does back to low. So the inputs are processed as long as the clock is high, but the output only changes on a falling edge.

I also read that other flip flops can be implemented using JK flip flops, which I'd understand if this circuit did not behave that way. With this circuit, if I connect J and K to a common input and invert the signal comming into K, as to implement a D FF, then the resulting circuit does not behave in the same way as the D FF I described earlier. Instead here is what the output does


Having a circuit only acknowledges inputs on a clock edge is a desirable property, but this JK FF that is shown everywhere seems to not work that way. But again I only learned about them recently so maybe my confusion comes from the fact that I am missing something. Is this behaviour normal or accepted for an edge-triggered flip flop? And is there a way to change the circuit so that the inputs are only processed during a falling or rising edge of the clock?

  • \$\begingroup\$ look at the J, K and Clk inputs to the first two nand gates and think about the outputs of those two gates ... you will realize that the J, K and Clk inputs are interchangeable \$\endgroup\$
    – jsotola
    Commented May 13, 2020 at 22:54

2 Answers 2


You have discovered the drawback of the Master-Slave JK flipflop.

The M-S JK flipflop is not edge triggered, it is pulse triggered.

What you have discovered is a phenomenon which M-S JK flipflops suffer from known as 'ones catching'.

This is when noise on the J or K inputs whilst the clock is high can alter the resulting outputs of the flipflop.

To avoid this drawback of the M-S JK flipflop the clock pulses should be kept short or avoid Master-Slave flipflops altogether and use true edge triggered ones.


You could look up 'ones catching' for more info.

  • \$\begingroup\$ Oh I see, so it is not edge-triggered after all, there was my mistake. I was certain there was something to it but the sources I am learning from did not mention this, and without knowing the name of this phenomenon I had trouble looking up info about it. \$\endgroup\$
    – Thomas.M
    Commented May 13, 2020 at 16:26
  • \$\begingroup\$ There is some confusion about this. Some sources refer to it as being edge triggered, others refer to it as pulse triggered. But the reality is that the first stage responds on the rising clock edge and the second stage responds on the falling clock edge, so a complete clock pulse is required for the outputs to respond - hence "pulse triggered". The problem, as you've found, is that the input stage will respond to positive going glitches on the J & K inputs whilst the clock is high. \$\endgroup\$
    – user173271
    Commented May 13, 2020 at 17:03

Both D type and JK type flip flops can be designed to trigger on either the positive or the negative clock edge.

However, perhaps for reasons of history, most 74 series TTL D type flip flops are positive edge triggered (74, 374, etc), and most JK type flip flops are negative edge triggered (112, 114 etc). Later families have tended to follow suit.

As a result, gate-level circuits published in teaching books may well be biased to show +ve edge Ds and -ve edge JKs.

  • \$\begingroup\$ Probably so, but that is not the source of my confusion. \$\endgroup\$
    – Thomas.M
    Commented May 13, 2020 at 13:43
  • \$\begingroup\$ @Thomas.M Perhaps I missed the point in your huge post then, what is the source of your confusion? Maybe a timing diagram would help illustrate it. \$\endgroup\$
    – Neil_UK
    Commented May 13, 2020 at 14:44
  • \$\begingroup\$ Yes it is pretty lengthy... I will add timing diagrams and try to make the post more concise as soon as I can \$\endgroup\$
    – Thomas.M
    Commented May 13, 2020 at 14:58

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