Simulating NMOS as capacitor example

Question

I would like to ask your opinion regarding NMOS test-bench as a varactor (voltage control capacitor). I am trying to find the properties of Vg,W for achieving a \$200fF\$ capacitor.

Here is my test-bench :

Calculated \$C\$ using AC analysis, where

\$C = \frac{I}{(V*2*pi*f)}\$

\$I = NMOS-Gate\$ point

and

\$V = voltage\$ on gate net.

Is this correct?

question - we are looking for \$Cgs\$ here, so can I just take the value from Cadence "Results Browser"?

Answer 1

The following is the equivalent circuit model of a FET. Disconsidering the parasitic inductances, if the drain and source ends are short citcuited the equivalent gate capacitance is given by:

$$C_{G}=C_{GS}+C_{GD}$$

source

The gate capacitance can be calculated by connecting a gate resistance much bigger than \$R_G\$ and sweeping the AC gate voltage according to the following e.g.:

1. Sweep AC gate voltage
2. Find the frequency at which the amplitude drops by 3dB
3. Workout the gate capacitance

In this case, the gate capacitance is given by:

$$C_{G(CALC)}=\dfrac{1}{2\pi\cdot23.4963kHz\cdot1k\Omega}\approx 6.77nF$$

It can be double checked by inspecting the model details:

$$C_{G(MODEL)}=5.2nF + 1.6nF=6.8nF$$