I have designed a simple 4-bit synchronous up-counter, using master/slave JK flip flops in Logisim.
Here is my JK design:
And my counter design:
It works perfectly as intended, however if the INC (count enable) is toggled to 0 while the CLK pulse is high - it doesn’t actually stop the count. Each successive clock pulse still increments the overall count, even though INC/count enable is now 0.
However, if INC is toggled to 0 while the clock pulse is low, it does indeed prevent the count from increasing. Am I missing something in the design?
I’ve tested this exact layout in other simulators too, so it’s definitely a flaw in the logic.
Note - PRE and NOT Q are the two unused pins on each JK chip in the counter circuit.