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I have designed a simple 4-bit synchronous up-counter, using master/slave JK flip flops in Logisim.

Here is my JK design:

Master/Slave JK Flip Flop

And my counter design:

4-bit synchronous up counter

It works perfectly as intended, however if the INC (count enable) is toggled to 0 while the CLK pulse is high - it doesn’t actually stop the count. Each successive clock pulse still increments the overall count, even though INC/count enable is now 0.

However, if INC is toggled to 0 while the clock pulse is low, it does indeed prevent the count from increasing. Am I missing something in the design?

I’ve tested this exact layout in other simulators too, so it’s definitely a flaw in the logic.

Note - PRE and NOT Q are the two unused pins on each JK chip in the counter circuit.

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The rising clock edge forces the first stage of the first flipflop to respond. Then INC goes low but the second stage of the first flipflop will still respond to the trailing (falling) edge of the clock pulse making Q0 change state. Q0 should then freeze at this new state because J & K have both been taken low.

You need to add some circuitry which will freeze the CLK in its current state when required to prevent the next falling or rising CLK edge.

A T-Type flip flop should do that made from a D-Type flipflop and an EX-Or gate.

T-Type Flipflop

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