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I have this problem:

Consider this circuit:

enter image description here

Find and describe the critical path. What is the maximum clock frequency?

MY ATTEMPT

Okay, this is how I see the critical path:

DFF -> G1 -> G3 -> DFF -> G4 -> DFF

The critical time can then be found with the given delay values:

\$t_{critical}=3(t_{cQ,prop})+3(t_{prop})+t_{SU} = 2(30 ps)+3(40ps)+10ps=190ps\$

The max clock frequency is then: \$f_{clk,max}=1/t_{critical}=\frac{1}{190ps}=5.26 \text{GHz}\$

Am I understanding this right? I spoke with one of my peers and he said that critical time is only between to registers and not through them.

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  • \$\begingroup\$ Those are clocked registers so everything is stopped at the register until the next clock cycle where it re-aligns temporally before moving on again. \$\endgroup\$ – DKNguyen May 14 at 13:17
  • \$\begingroup\$ Oh, so the cricitcal path is actually: DFF -> G1 -> G3 -> DFF. Making the critical time: t_cQ,prop + 2(t_prop) + t_SU. am I correct? \$\endgroup\$ – Carl May 14 at 13:29
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    \$\begingroup\$ Yes, I think so. I forget what most of the timing terms are though \$\endgroup\$ – DKNguyen May 14 at 13:30
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    \$\begingroup\$ @Carl - you may be right. I've been doing this for a long time and never heard that term before. Usually, on a data sheet, prop times are specified as Tcq (or some variation there of), with 3 columns to the right for min, typ, and max values. Sometimes you'll see Tcq(max), for example. Finally, on many data sheets, the min prop times is not specified at all. \$\endgroup\$ – SteveSh May 15 at 18:52
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    \$\begingroup\$ @Carl- By not specifying a min prop time, IC makers can take advantage of smaller geometries in the fab process, which almost always means faster devices, without having to update their documentation. If the Tcq(max) number is 10 ns, and a process improvement moves that down to 5 ns, nothing needs to change on the data sheet. \$\endgroup\$ – SteveSh May 15 at 19:12
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Those are clocked registers so everything is stopped at the register until the next clock cycle where it re-aligns temporally before moving on again.

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