I'm asking this because, while learning about how counters work, I read that one can add an input that enables or disables the counter depending on its logical value. Now, my first instinct would have been to AND the enable input with the clock signal, so that the Flip Flops of the counter are only clocked when the counter is enabled, like so


However, pretty much every source that I have found that teaches the principles of counters present this kind of circuit instead


Here, making enable low inhibits the inpts of all JKs so that they hold their state.

I understand that, from a purely logical standpoint, those two solutions are equivalent (in that they achieve the same goal), but I am curious to know why the second one is almost allways presented, and the first almost never (as far as I have seen at least). To me the first one seems more instictive, at least it's the one that came to my mind immediately. But more importantly, it also seems to be simpler to implement in practice since it only requires one additional gate, whereas the second one requires an amount that grows with the width of the counter.

Considering that, is there a practical reason to favour the second circuit over the first one? I know almost nothing of the physical, electrical, side of digital designs (i.e. things that have to do with stray capacitance or inductance, or phenomenons that occur at high or low frequencies, component wear, etc), so if something is going over my head I'm guessing it has to do with that.

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    \$\begingroup\$ Timing. The first delays the clock by one gate delay, putting it out of sync with the rest of the design. At he very least, analysing whether it'll work becomes much more difficult; often the result of that anaylsis is : NO. \$\endgroup\$
    – user16324
    May 14, 2020 at 12:44
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    \$\begingroup\$ another reason is that if the enable transitions when the clock is high, the counter will advance when it shouldn't \$\endgroup\$
    – Neil_UK
    May 14, 2020 at 12:59
  • \$\begingroup\$ I see, it was simpler than I thought, thanks \$\endgroup\$
    – Thomas.M
    May 14, 2020 at 14:05
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    \$\begingroup\$ The other part is noise on the enable signal can be modulated on top of the clock signal. E.g. you switch the enable signal faster than the clock while it is high. The second method does not care because the clock has not yet transitioned. Where the first does. \$\endgroup\$
    – Reroute
    May 14, 2020 at 14:58

2 Answers 2


[...] is there a practical reason to favour the second circuit over the first one?

Yes. The first approach is known as "gating the clock", and one of the cardinal rules of robust synchronous logic design is to avoid this practice. There are many helpful answers and comments about this in the related topic What does it mean to "gate the clock"? For example:

Not gating clocks is good advice. It can be done, with care and thorough understanding of the possible consequences. These include metastability when taking clocked signals into the gated clock domain and worse results from timing-driven synthesis/layout.

But there are nearly always other ways to achieve the same control over a circuit as gating the clock, without all such risks and penalties.

As these answers (and others) hint, a designer certainly can gate the clock, and some designers will do it for reasons of reducing power draw and the like. But unless there is a compelling reason otherwise, the preferred approach is to always keep the clock signal itself pristine. This is the easiest/simplest approach to get a solid, stable, robust design.


In a digital system, a clock is a very 'special' signal that one must take great care with. We'd like to leave clock network clean, avoiding any unnecessary logic. I do insert clock gating cells manually at some places in practice. (Use ICG cells provided by the standard cell library. Using & or | in your HDL code and let the synthesis tool map to gates is not recommended.) But this is done in system level, in a 'static' sense. That means we put these clock gating cells only in system or sub-system level clock management block that one gate cell can shut down the clock supply to plenty of hardware logic, say an image processing module with many many gates. User (or software) can shut down the clock if the image processing module will not be in use for a long time to reduce power consumption.

There's another kind of clock gating controlled by synthesis tool. We don't recommend gating clock manually in a block level or somewhere the circuit is enabled/disabled 'dynamically', like what is described in your question. Just code the logic portion, and let the tool handle the rest.


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