I'm asking this because, while learning about how counters work, I read that one can add an input that enables or disables the counter depending on its logical value. Now, my first instinct would have been to AND the enable input with the clock signal, so that the Flip Flops of the counter are only clocked when the counter is enabled, like so
However, pretty much every source that I have found that teaches the principles of counters present this kind of circuit instead
Here, making enable low inhibits the inpts of all JKs so that they hold their state.
I understand that, from a purely logical standpoint, those two solutions are equivalent (in that they achieve the same goal), but I am curious to know why the second one is almost allways presented, and the first almost never (as far as I have seen at least). To me the first one seems more instictive, at least it's the one that came to my mind immediately. But more importantly, it also seems to be simpler to implement in practice since it only requires one additional gate, whereas the second one requires an amount that grows with the width of the counter.
Considering that, is there a practical reason to favour the second circuit over the first one? I know almost nothing of the physical, electrical, side of digital designs (i.e. things that have to do with stray capacitance or inductance, or phenomenons that occur at high or low frequencies, component wear, etc), so if something is going over my head I'm guessing it has to do with that.