# How to synchronize a DAC?

How can I reduce the delay happening between writes to the DAC (as shown below)?

The yellow represents how long the DAC writes last for which is 232.9us The green represents the output from the DAC, if zoomed in you will see a 16.30kHz sine wave.

After the first DAC write (0 - 1024) there's a 15.4ms delay until the second write occurs which is also shown below.

It takes ~232.9us to write 1024 values into the DAC. How do I close this 15.4ms gap and make it transition to the second write much cleaner? I was thinking using perhaps timers?

The way I have the DMA set up is as follows:

• When the ADC detects an incoming signal DMA starts sampling
• The DMA will first sample 1024 values this takes 15.7ms
• Once done it will request a half complete interrupt where then I start my first DAC writes
• the DMA will sample the other 1024 values as this takes 15.7ms as well
• Once done will request a complete interrupt then I start my second DAC writes

Code:

void DMA2_Channel3_IRQHandler(void){

if (((DMA2->ISR) & (1<<10)) != 0){ // Check to see if the Half Complete Flag is set
halfTransferComplete = 1;
DMA2->IFCR |= (1<<10);
} else if (((DMA2->ISR) & (1<<9)) != 0){ // Check to see if the Complete Flag is set
transferComplete = 1;
DMA2->IFCR |= (1<<9);
}
}

int main(void) {

while (1) {

if (halfTransferComplete == 1){ //Stays in this block of code for 15.7mS
GPIOA->BSRR = 1<<0;
for (int i = 0; i < 1024; i++){
}

GPIOA->BSRR = 1<<16;
halfTransferComplete = 0;
}

if (transferComplete == 1){ //Stays in this block of code for 15.7mS
GPIOA->BSRR = 1<<0;
for (int i = 1024; i < 2048; i++){
}

GPIOA->BSRR = 1<<16;
transferComplete = 0;
}
}
}


• Comments are not for extended discussion; this conversation has been moved to chat. – Voltage Spike Jun 13 '20 at 4:18