I am new to the concept of Single Stage amplifiers design using CMOS. In that, I came across a concept of using current source as loads in design of Common Source Stage, where it was mentioned in a statement that, the PMOS current source as load is generally preferred than using NMOS current source as load in Common Source stage. May I know the actual reason for this statement. If there is any reference available related to my question, kindly share it.
In general analog CMOS IC design (general normal speed opamps, comparators, circuit where noise is not a problem, so on) it does not really matter, if only you do not have such design that needs to be extremely noise aware, RF or of other reasons. In reality, for example during opamp design (where such CS stages are used), you get other requirements that you need to satisfy as input voltage range. That determines you the NMOS or PMOS input differential pair what then determines you the PMOS or NMOS Common Source Stage which is 2nd stage in opamp class A architecture:
Source: https://payhip.com/b/5Srt ("Preview" button in top right corner)
Second stage (marked green) of above opamp architecture is Common Source Stage with NMOS current source load. NMOS current source load of 2nd stage was determined by using opamp classical class A architecture with NMOS input differential pair M1-M2. If PMOS differential pair is used in the above architecture, the 2nd stage is constructed by Common Source Stage with PMOS current source load.
Either n or p may be used as load or driver depending on spec as the devices are mostly complementary. IC technology builds both nmos and pmos devices in the same substrate however and as a result, the devices will have different behaviour-- n and p thresholds and mobility will be different so that one device may be 'better' than the other, depending on technology. For the same geometries in most technologies, the electron (n) generally will have a larger mobility than the hole (p) resulting in larger transconductance, gm, for nmos than that for the pmos. Devices will not be symmetric. This is why we generally scale the pmos wider than the nmos to get similar rise and fall times in simple logic gates. (Leading technologies in sub-micron go to great lengths to match the n vs p performance.) To get the highest performance design you will want to use the faster device as the driver, slower for load, for example. Another design however, will need to drive closer to one rail than the other. This will define which device to use where. Noise considerations add another design consideration. So, in general, a designer matches device to requirement taking the differences between n and p behaviour into consideration.