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Background -- I have in my possession a schematic for an ASIC NMOS chip developed between around 1985 until 1992. It's copyrighted and I'd rather not get into the details of of what its for, but my goal is to capture the schematic and convert it into Verilog as accurately as possible to preserve a "perfect" copy of the chip.

Most of the logic is very straght forward, however, there are times when a gate is drawn in parallel with the output of the first gate tied to the 'bubble' of the second. Here's a pic:

Picture of two NOT gates in parallel with output of one tied to the 'bubble' of the next

This same schematic uses this same parallel structure for other gate types, such as this:

enter image description here

It's also not a tristate enable, as that shows up on the schematic, as shown here for driving an output pad:

enter image description here

As always, thanks for the help.

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    \$\begingroup\$ What's the context? In who's schematics did you find it? \$\endgroup\$
    – Transistor
    May 15, 2020 at 20:05
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    \$\begingroup\$ We need context like part numbers ... but as a guess : the lower device may eb an inverter with a 3-state output controlled by an enable input drawn as connecting to the bubble. \$\endgroup\$
    – user16324
    May 15, 2020 at 20:09
  • \$\begingroup\$ This is from an old 80's era NMOS chip. I'd like to avoid the specifics of the original chip model or manufacturer if I can. \$\endgroup\$ May 15, 2020 at 20:18
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    \$\begingroup\$ While I am not sure, the picture just looks like two identical gates in parallel. Maybe to increase drive strength or something like that. It is, maybe, a bit odd that the connection is specifically to the bubble and not to the line after the bubble. But I still think it is just two gates in parallel. (only guessing) \$\endgroup\$
    – user57037
    May 15, 2020 at 22:04
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    \$\begingroup\$ Depending on just how imperative it is that you clone this chip, it might be worth getting ahold of one and decapping it to see if you can see the actual structure of these gates in the silicon itself. That's not a simple process, but if it's a chip of historical significance or one that you're otherwise willing to go to that much effort for (or can find someone else who would go to that effort instead), it could be a good thing to look into. \$\endgroup\$
    – Hearth
    May 16, 2020 at 13:53

2 Answers 2

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They are directly in parallel, just drawn weirdly, usually this is to increase the amount of current that can be driven over just a single not gate, they would normally have some series resistance on the outputs, but in some cases can get away without it (the mosfet capacitance takes longer to discharge than the maximum difference in gate delays)

for the application they are in, a mosfet gate drive, the faster you can charge / discharge the gate, the sharper the transition, and possibly less heat generated during the transition, equally the NOR gates are in parallel for the same reason, to increase how quickly it can switch the mosfets.

For some fast pulse sources e.g. for time domain reflectometery you may also find similar, with 6,8,10 or more in parallel to give a very fast transition on a capacitive load.

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It's really hard to say for sure what those connections mean. If this is an ASIC from the mid 80's, it means it was designed before HDL tools based on Verilog or VHDL came into wide use. So it was probably designed with a schematic-based tool, with symbols and models provided by the ASIC vendor. Those symbols relate to basic functional building blocks the ASIC vendor uses. There is not necessarily a one-to-one relationship between commodity digital parts (like 5404 inverters) and the "parts" that show up on an ASIC schematic.

Note that this design flow was not unique to ASICs. FPGA vendors like Xilinx also provided a schematic-based design flow using schematic symbols unique to the FPGA manufacturer's product line.

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