Background -- I have in my possession a schematic for an ASIC NMOS chip developed between around 1985 until 1992. It's copyrighted and I'd rather not get into the details of of what its for, but my goal is to capture the schematic and convert it into Verilog as accurately as possible to preserve a "perfect" copy of the chip.
Most of the logic is very straght forward, however, there are times when a gate is drawn in parallel with the output of the first gate tied to the 'bubble' of the second. Here's a pic:
This same schematic uses this same parallel structure for other gate types, such as this:
It's also not a tristate enable, as that shows up on the schematic, as shown here for driving an output pad:
As always, thanks for the help.