0
\$\begingroup\$

Circuit made in TinkerCadI created an emitter-follower circuit on a breadboard using TinkerCad. The circuit is based in the LTSpice simulation of the said circuit. According to the simulation, the input and output voltage waveforms should be in phase. But when I tried to construct the same circuit on TinkerCad, the scopes' readings do not seem to show that the waveforms are in-phase. Is there something wrong with the constructed circuit in the TinkerCad version?

\$\endgroup\$

3 Answers 3

1
\$\begingroup\$

The TinkerCad scope traces show no indication of being phase matched. I suspect they both 'trigger' at the AC center of the waveform. Since the output waveform has its bottom half cut off, the scope trace is triggered half way up the positive half which makes it appear to have a phase lead.

Try adding a DC bias voltage (lower knob) of about 8.2 V (15 V / 2 + 0.7 V) to the input signal. This should make the output a sine wave and the apparent phases similar. If it has the option of two traces on one scope then use that.

\$\endgroup\$
0
\$\begingroup\$

Rule #1: Vbe must always be positive and > 0.6 for good conduction.
Rule #2: Ensure signal keeps base and emitter biased correctly. Vbe> 0.6, Ve < Vcc-0.5 (depending on % of rated current)
Rule #3: Source Impedance ought to be << 10% of load= hFE*Re , including caps
Rule #4: List expectations for frequency response with load (Z(f) or R+C)
Rule #5: always consider gain and offset voltage in your design specs for ANY AMP

Example enter image description here

I also demonstrate the Falstad Sim with some very useful probes which can be awkward in placement of the text, but are rather accurate. If -ve is floating, it is assumed =0V. You can choose Min,Max,Vpp,Vrms.

Shown is the menu for the Voltage Scope Probe.

Result:

I chose R pullup = 50x Re and R base to ground-= 100x Re to reduce the attenuation from base to emitter. The biggest loss here is actually from the 50 Ohm generator that I created, starting with 5Vp. (10Vpp) and ending up with 9.386 Vpp. Results depend on your specs. This can be improved or made worse.

Simple Answer

In your case you have ;

Rs= 270 , Re= 3k3

Add a pullup R from Vb to Vcc which also attenuates Vac input

add Rpu=540 = 2*Rs

Now what do you get?

\$\endgroup\$
-1
\$\begingroup\$

Why is output scope shifted in phase? The Tinkercad scope widget behaves like an 'AC' trigger on a real scope: it finds a midpoint and starts the trace there.

  • Input trace, symmetrical waveform: trigger at zero cross
  • Output trace, asymmetrical waveform: Trigger halfway up the positive swing

Because Tinkercad scope on the output triggered later in the waveform than the input, it missed the first part of the wave. This introduced the phase shift relative to the input.

You didn't see this in LTSpice because that simulator starts displaying all the waveforms at the same time, from the beginning of the sim. (You'll see below that Falstad does the same thing.)

How to fix it? I don't know if Tinkercad has the ability. The scope widget needs to support multiple traces with a common trigger so that they can be shown correlated in time. This is how such an issue would be solved with physical scopes.

Maybe time to use a different sim tool then, or complain to Autodesk to have them fix it?


Now, about that asymmetrical output... let's workshop that a bit.

tl; dr version: that emitter follower you've built is broken. How? In two ways. One way is a gross error, and the other more subtle.

First the gross error. The Vin signal is referenced to 0V, so the follower is only functioning on the positive half-cycle. The rest of the time the transistor is off. That's why the output looks like a half-wave.

It's actually even worse than that: the peak is about 0.7V less than the input. Why? For the transistor to turn on, it needs to see its base voltage be above its minimum base-emitter forward voltage, or Vbe, for base current to flow. Vbe minimum forward voltage is about 0.7V.

To fix this, the input signal must be offset so that its swing takes it no lower than Vbe, that is, 0.7V, ensuring the base is in forward bias for the entire signal range. We can do that by adding a DC offset to the input signal; this is possible in Tinkercad using the signal generator DC offset knob.

For a signal with a 15V peak-to-peak input, we compute an offset as follows:

  • Vin offset = V(pk-pk)/2 + Vbe = 15/2 + 0.7 = 8.2V

We crank in the DC offset of 8.2V and get closer to the expected result: a symmetrical sine. The 'phase shift' problem you're asking about goes away too.

Here's your circuit, with this change, in Falstad (simulate it here):

enter image description here

Great, we've fixed the signal offset and got the Vbe bias right, and output looks kind of ok, but there's still an issue. Can you see it? Look at the output peak. It's flattened at the top.

This leads us to the second, more subtle thing that's wrong. The transistor is clipping on the positive peak. Why? The transistor is being driven all the way to its minimum collector-emitter voltage, called Vce(sat), or collector-emitter saturation voltage. Vce(sat) varies depending on the collector current, but is typically about 0.2 to 0.6V.

How to fix that? Either increase the +15V slightly (to about 15.6V) to allow for Vce(sat), or decrease the signal a bit.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.