Why do I get a Top Level Design Entity undefined in my VHDL

Question

I'm building an 8-bit register from d-type flipflops in VHDL for a lab exercise but I can't seem to diagnose a problem. Firstly I can't get it to compile because of the difference in types for the input clock. My project is called eightBitRegister so its not because my definition uses a different name. So if I change this to the correct type I get the error:

Error: Top-level design entity "eightBitRegister" is undefined

The VHDL when this occurs looks like:

LIBRARY ieee ; 
USE ieee.std_logic_1164.all ; 

ENTITY eigthBitRegister IS 
PORT ( Clock: in BIT;
       Data:  in BIT ; 
       Q: out BIT) ; 
END eigthBitRegister ; 

ARCHITECTURE Behaviour OF eigthBitRegister IS    
COMPONENT flipflop is 
PORT ( D: in BIT ; Clock: in BIT;
      Q: out BIT) ; 
END COMPONENT; 

SIGNAL QOut: BIT_VECTOR(7 downto 0);

begin

Stages: for i in 7 downto 0 generate
LowBit: if i = 0 generate
    ff:flipflop PORT MAP(Data, Clock, QOut(0));
end generate; 

OtherBits: if i /= 0 generate
    ff:flipflop PORT MAP(QOut(i-1), Clock, QOut(i));
end generate;
end generate;

Q <= QOut(7);
END; 

However if I change it to this:

LIBRARY ieee ; 
USE ieee.std_logic_1164.all ; 

ENTITY eigthBitRegister IS 
PORT ( Clock: in STD_LOGIC;
       Data:  in BIT ; 
       Q: out BIT) ; 
END eigthBitRegister ; 

ARCHITECTURE Behaviour OF eigthBitRegister IS    
COMPONENT flipflop is 
PORT ( D: in BIT ; Clock,
      Q: out BIT) ; 
END COMPONENT; 

SIGNAL QOut: BIT_VECTOR(7 downto 0);

begin

Stages: for i in 7 downto 0 generate
LowBit: if i = 0 generate
    ff:flipflop PORT MAP(Data, Clock, QOut(0));
end generate; 

OtherBits: if i /= 0 generate
    ff:flipflop PORT MAP(QOut(i-1), Clock, QOut(i));
end generate;
end generate;

Q <= QOut(7);
END; 

It can find the top-level identity and get the error:

Error (10476): VHDL error at eightBitRegister.vhd(22): type of identifier "Clock" does not agree with its usage as "bit" type

So whats going wrong?

Answer 1

Your error says: eightBitRegister, but your code says: eigthBitRegister.

( ht vs th )

So you are probably trying to instantiate an entity that does not exist as spelled.

The second error is just a type error you introduced (bit vs std_logic), but the entity has not been found yet either, the compiler is just now stopping at this new error, before it gets a chance to get to the other one.

Answer 2

"Error: Top-level design entity "NAME" is undefined"

This is what I did to correct.

1. check paths for spaces, none allowed.
2. check entity name can not start with number.
3. Assignment - Settings - General - Top-Level Entity - "..."
4. From bottom up. select next entity up. Apply - OK.
5. Processing - "Start Compilation"
6. When complete. Tools - "Netlist Viewers" - "RTL Viewer" Don't know if this step is necessary. It's what I did.
7. Repeat from step 3) moving up for each entity in list.
8. when finished, one last time with first (bottom/original) "Entity Name"
9. Done

This created what was missing that was needed. I worked for me hope it works for you.