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Is there an easy way to explain this process to a non-expert? I read many places but couldn't figure out. I can understand the job of PLL which locks the output frequency to the fed back frequency hence can be used to increase the frequency of an oscillator stability.

But what is meant by clock recovery(wikipedia didnt help) and how does a PLL recover the clock from digital data signals (CDR)? Is there a easier way to explain this as a big picture?

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In music, imagine counting the beat of a song while listening to the drumbeat in a song. But what if the the drum beat was ocasionally skipped in the song? Would you suddenly lose the beat? Probably not. Not for a while at least. You could keep counting the beat in your head through the skipped drum beats and you would still be fairly accurate. At least for a while. The next time you hear the drum beats sounds you readjust your counting so you never get too far off as long as you don't go for too long without the drum. Same thing.

Fundamentally a PLL is something that oscillates by locking onto another oscillation and matching its phase, and when that oscillation isn't there, the PLL can continue to oscillate on its own. It doesn't need to multiply frequency although it can (just like how you can try and count every quarter note even when the beat of a song might only sound every whole note).

A serial datastream with an embedded clock has edge transitions that are synchronized to whatever clock was used to generate it, but these edges aren't always there since the datastream needs to actually carry information. It isn't just a clock signal. So you might get something with multiple zeroes or ones in a row where you an edge isn't there. When you do, the PLL keeps counting on its own and whenever an edge comes the PLL resynchs to it. That way, you extract a clock signal from the datastream and always have a clock present.

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