Creating a majority gate using only NOR gates

I have this digital logic circuit homework and I've been trying to solve it for a day and in the end I got a wrong answer. Here is the question:

Create a majority gate using only NOR gates, with 4 inputs a,b,c,d. Which means the output will be 1 if the majority of inputs are 1.

I draw the truth table and Karnaugh map, but they weren't helpful really.

The logical expression will be: a'bcd + ab'cd + abc'd + abcd' + abcd.

If we simplify it we will get: bcd + acd + abd + abc.

I tried to simplify it to a NAND form and I got a very long expression which was not true(I checked it with Proteus).

Can anyone help me please?

• Can you show your work (how did you reach this expression you're talking about and your NAND form)? Also, a "majority gate" with 4 inputs seems strange: what is its output if there are two 0s and two 1s? May 17, 2020 at 20:31
• I reached to this expression using truth table, and then I complemented the whole expression twice( I mean like a") and simplified it in some steps. May 17, 2020 at 20:46
• If there are two 0s and two 1s, the output will be zero I think. I saw the truth table on the internet (images.app.goo.gl/MijAcKLH9gd312jN8). May 17, 2020 at 20:49

1 Answer

You can implement any logic circuit using only NANDs, it doesn't mean you will use a single NAND. Try writing down how to implement the following logic gates using NANDs

• AND
• OR
• NOT

With those you can definitely implement the function you have, but simplifying it will require either manipulating the boolean expression bcd + acd + abd + abc to write it with NANDs or using Karnaugh maps (but it is a bit different than the one for AND/OR simplification).