I'm having problems contracting, in CADENCE for some modification that I can't use the layout, I normally did the INVERTER and AND ports, but when I get to the NAND port there are some errors, a message about the library (I'm using the correct library ), it does not look like the components even with the option GENERATE ALL FORM SOURCE and the metals are not in the list. See the image.
Thanks to everyone, a friend explained how to resolve and the reason for the error.
Solution: In the library where the folder you are working in (saving the files) must delete all files by calling cdslck.
One of the reasons for the failures: When CANDECE closes in an inspired fashion or executes the shutdown in the wrong way regardless of whether you are running on remote access or on the spot, the cdslck file will appear, according to him, which says that it is a protection measure not to lose the projects.
See the image to facilitate what was said. There are two ways to do this: 1st folder per part to delete cdslck or 2nd go to the search engine and delete all cdslck at once.
Note: You must exclude all files by calling cdslck (with their derivations).