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This is my verilog code. Though I am not getting any output, if any two of the instantiated modules are commented then I am getting proper partial output(For full output I need all of them to work). But all three as simulated together then the variables are as if they haven't been instantiated. All of the calculations are for Posit Numbers. I will send the link for understanding this number format. I have to perform:x1=xin2 and then x2=1-x1tmp(this is where I am using x1tmp=-x1) and finally err=xx2. Over all I have to perform err=x(1-x*in2).

    module check(x, in2, err, start);//x and in2 are inputs for this module and //err is the output.Start is the signal given from testbench for starting this module
    parameter N = 32;// This is the bus width for all the variables.
    parameter es = 3;// This is the parameter required for calculating 
    input       [N-1:0]x;
    input   [N-1:0]in2;
    output  [N-1:0] err;
    wire        [N-1:0] x1;//These are nets declared for intermediate calculation
    wire        [N-1:0] x2;//Same as that of x1
    wire        [N-1:0] oru = {{(3){1'b0}},1'b1,{(N-4){1'b0}}};// This is "1" in //posit number format
    posit_mult #(.N(N),.es(es)) m1(x, in2, start, x1, inf, zero, done);//x1=x*in2, where the rest of them are status signals(1-bit)
    wire        [N-1:0] x1tmp = -x1;//To get 2's complement of x1
    posit_adder #(.N(N),.es(es)) a1(x1tmp, oru, start, x2, inf, zero, done);//x2=x1tmp+oru
    posit_mult #(.N(N),.es(es)) m2(x, x2, start, err, inf, zero, done);//err=x*x2
endmodule

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The mistake I did was using same status signals for multiple instances. I sincerely thank @toolic for helping me out. The italicized signals in the code should have been distinct for each module, because of using same variables it caused contention.

module check(x, in2, err, start);//x and in2 are inputs for this module and //err is the output.Start is the signal given from testbench for starting this module
    parameter N = 32;// This is the bus width for all the variables.
    parameter es = 3;// This is the parameter required for calculating 
    input       [N-1:0]x;
    input   [N-1:0]in2;
    output  [N-1:0] err;
    wire        [N-1:0] x1;//These are nets declared for intermediate calculation
    wire        [N-1:0] x2;//Same as that of x1
    wire        [N-1:0] oru = {{(3){1'b0}},1'b1,{(N-4){1'b0}}};// This is "1" in //posit number format
    posit_mult #(.N(N),.es(es)) m1(x, in2, *start*, x1, *inf*, *zero*, *done*);//x1=x*in2, where the rest of them are status signals(1-bit)
    wire        [N-1:0] x1tmp = -x1;//To get 2's complement of x1
    posit_adder #(.N(N),.es(es)) a1(x1tmp, oru, *start*, x2, *inf*, *zero*, *done*);//x2=x1tmp+oru
    posit_mult #(.N(N),.es(es)) m2(x, x2, *start*, err, *inf*, *zero*, *done*);//err=x*x2
endmodule

This can be solved either by using distinct variables or by removing them(if they are not useful) as:

module check(x, in2, err, start);//x and in2 are inputs for this module and //err is the output.Start is the signal given from testbench for starting this module
    parameter N = 32;// This is the bus width for all the variables.
    parameter es = 3;// This is the parameter required for calculating 
    input       [N-1:0]x;
    input   [N-1:0]in2;
    output  [N-1:0] err;
    wire        [N-1:0] x1;//These are nets declared for intermediate calculation
    wire        [N-1:0] x2;//Same as that of x1
    wire        [N-1:0] oru = {{(3){1'b0}},1'b1,{(N-4){1'b0}}};// This is "1" in //posit number format
    posit_mult #(.N(N),.es(es)) m1(x, in2, , x1, , , );//x1=x*in2, where the rest of them are status signals(1-bit)
    wire        [N-1:0] x1tmp = -x1;//To get 2's complement of x1
    posit_adder #(.N(N),.es(es)) a1(x1tmp, oru, , x2, , , );//x2=x1tmp+oru
    posit_mult #(.N(N),.es(es)) m2(x, x2, , err, , , );//err=x*x2
endmodule
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For code review, I have reformatted and added comments that reflect my partial understanding of this code. One thing that makes this type of code difficult to read and understand is that the port names do not give any hint whether they are input or output. Since this is a toplevel module only, I can only guess about the signature of the submodules and the semantics of the ports. There was a comment about MCVE (Minimal, Complete, Verifiable Example), there's a limit to what can be seen with just one module missing the submodules.

I suspect that the problem is somewhere in the undeclared, implicit connections of the ports inf, zero, and done. With no explicit definition of these wires, Verilog will assume that these are single-bit wires.

Recommendations

I recommend you examine the RTL output of translation phase, very likely something is going wrong at that level. See my other answer about using RTL as a diagnostic here: https://electronics.stackexchange.com/a/497663/35022

Reading and understanding another person's code is always hard, hopefully you can see from the gaps in my comments the areas that can be unclear. Even for homework, it's good to develop the habit of explaining through variable names and brief comments what each module, wire, and reg is supposed to be doing. The module itself should also have a standard block comment, explaining in a few sentences or a paragraph what the module is intended to accomplish.

The style of indentation that I'm using here is one that I use on larger projects, having many more parameters and ports. I use indentation to help distinguish input ports from output ports. Usually I also append a suffix of _i, _o, or _io to port names in the modules, to further distinguish inputs from outputs. Wires themselves are neither input nor output, but there should be exactly one output driver connected to each wire (unless it's some tricky tri-state wire scheme).

// https://electronics.stackexchange.com/questions/500439/i-am-trying-to-instantiate-few-modules-to-work-in-top-level-design-but-even-tho
// code review https://electronics.stackexchange.com/users/35022/marku
//
// Module check
// navaneet rao https://electronics.stackexchange.com/users/252818/navaneet-rao
// licensed under cc by-sa. rev 2020.5.18.36843
//
// testbench for module posit_mult and module posit_adder.
// usage: set up data inputs x and in2, then enable with a high level on start.
// there is no clock, this is all combinational logic.
// expect output port err should report ???____??? if all is well.
//
module check(x, in2, err, start);
parameter N = 32; // data width
parameter es = 3; // ??? not sure what this is, but it is passed to the submodules
// input/output port declaractions
input   wire [N-1:0] x;
input   wire [N-1:0] in2;
input   wire         start; //Everything is explained in the below module.
                            // ???
output  reg  [N-1:0]         err;    // driven by instance m2

// internal connection wires
wire [N-1:0] x1; // driven by instance m1

wire [N-1:0] x2; // driven by instance a1

wire [N-1:0] oru = {{(3){1'b0}},1'b1,{(N-4){1'b0}}};

// wire inf;  // ??? implied, not declared, is this a 1-bit wire or a reg?
// wire zero; // ??? implied, not declared, is this a 1-bit wire or a reg?
// wire done; // ??? implied, not declared, is this a 1-bit wire or a reg?

// internal submodule declarations
posit_mult #(
    .N(N),
    .es(es)
) m1 (
    x,      // driven from toplevel
    in2,    // driven from toplevel
    start,  // driven from toplevel
        x1,     // output
            inf,    // ??? what drives this wire?
            zero,   // ??? what drives this wire?
            done    // ??? what drives this wire?
);

wire [N-1:0] x1tmp = -x1; // x1tmp is 2's complement negation of x1

posit_adder #(
    .N(N),
    .es(es)
) a1 (
    x1tmp,  // 2's complement of x1 driven from toplevel
    oru,    // constant input
    start,  // driven from toplevel
        x2,     // output
            inf,    // ??? what drives this wire?
            zero,   // ??? what drives this wire?
            done    // ??? what drives this wire?
);

posit_mult #(
    .N(N),
    .es(es)
) m2 (
    x,      // driven from toplevel
    x2,     // driven from instance a1
    start,  // driven from toplevel
        err,    // output
            inf,    // ??? what drives this wire?
            zero,   // ??? what drives this wire?
            done    // ??? what drives this wire?
);

endmodule
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  • \$\begingroup\$ Sir, I have edited my post if any further clarification is required, please let me know. Kindle requesting your help. Thank you. \$\endgroup\$ – navaneet rao May 19 '20 at 7:41

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