Signal line current estimation and impedance matching

Question

As far as I know, the input pins to ICs are typically just the gate of a MOSFET. I have always just take stuff for granted (like if you want to control a logic pin, just put a source voltage on it), but recently I have been thinking about how these things actual connect.

1. How do I estimate the current level going through the signal line? For example,if I have a driver outputing a high frequency control signal to an IC, how do I estimate the instanteous or effective current going through this path so I can size my PCB trace appropiately? In my mind, the MOSFET will ask for as much current possible to charge and discharge the gate, so it could be pretty bad if the driver is capable of high current (1 A) but the trace is not sized properly. If the driver is limited, I don't think it is available in all IC datasheet so I want to understand what people do to ensure the signal trace is appropiately sized for power. I know some people will put a gate resistor to limit current and therefore transition time, but it is not the best to minimize FET power lost.

2. For signal lines, would the general design consideration is that you want to match impedance for signal integrity while making sure the trace can handle the required current?

Let me know if I am understanding it correctly!

Thanks!

Answer 1

for your first question, I think considering the capacitance of this gate you mention will let you shape how the current pulse will look, if you are not adding a resistor, I would use the trace resistance and simulate the gate capacitance charging. This will look close to the actual gate current of the device in the transient region.

for your second question, depends on what you want to do... without knowing the whole goal of the board it is hard to give design pointers, I mean it is common also to try and lower inductance when you can, but some power converters want to add inductance on purpose in some cases(few, but they exist)

I don't think there is a hard rule that applies to all boards that can ignore the goal of it.

Answer 2

FET gates live behind the PCB impedances, the IC package inductances, the bond wire inductance, and the various (1pF?) parasitic capacitances, plus the onchip ESD capacitances.

And the FET gates, even if metal gate, will always reside above doped silicon that must be inverted to form a channel; so even if the gate material is mtal, the other plate of the gate capacitance will have "well" resistance to limit the charging currents.

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Estimating the peak charging currents: assume 5 volt logic swing, 1 nanosecond ramp, 10 picofarad load.

• using the math I = C * dV/dT

we have

• I = 10 pf * ( 5v / 1 nanosecond)

Combining the "pico" with "nano" to produce "milli"

• I = 10 * 5 * milli === 50 milliAmps.

Given the electrical length allows 1nanosecond distance (approximation, here), then this current --- 0.050 amps --- should be observable on a PCB with an inch or two inches between your fast logic ICa. Here the "lumped circuit model" is valid model.

by the way, 100pf is a more reasonable value for PCB plus short cables plus IC output/input pins. But this is no longer a "lumped circuit model", unless all the capacitive loading is within a few inches of the Driver IC.

If you do have 100pF loading all within a few inches of the Driver IC, you should expect major collapse of your VDD rail, at least inside the Driver IC.

That is because of this inductive effect:

• V_rail_collapse_IC = L * dI/dT

with L = 5nh, dI = 0.5 amps, dT = 0.5 nanosecond

• Vrail_collpse_IC = 5nH * 0.5 / 0.5nS = 5 volts drop in on_chip VDD.

Hence for such output currents, you should use Multiple VDD/GND pairs, as you will notice on FPGA pinout diagrams.