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I am about to write a TCP/IP stack in Verilog. I would have thought this was a relatively common thing, and that implementations would readily be available online.

The obvious Google search for a TCP/IP implementation in Verilog does not point to many solutions. Are there ready and tested TPC/IP implementations written in Verilog for FPGAs?

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    \$\begingroup\$ Could you use one written in vhdl? \$\endgroup\$ – apalopohapa Nov 28 '12 at 18:16
  • \$\begingroup\$ @apalopohapa: Would prefer not! \$\endgroup\$ – Randomblue Nov 28 '12 at 18:16
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    \$\begingroup\$ While this is theoretically possible, it's probably not a great idea. TCP is much more a procedural and decision making task, than a primitive/fast/parallel one, so it is more suited to a sequential processor running a program, than it is to state machines and dedicated logic. You could throw in a processor core, but then you'd have to store the program. \$\endgroup\$ – Chris Stratton Nov 28 '12 at 20:22
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They exist, but aren't likely to be free. Typically a processor handles TCP/IP. It may get a hardware assist from hardware, for example the checksum.

An example of a non-free one is from Hitech Global. It is available in Verilog or netlist. Comblock has one too, but in VHDL, not Verilog.

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    \$\begingroup\$ Accelize has one, intilope has one... Some good IP(s) will cost you around $30K. \$\endgroup\$ – user8459 Nov 28 '12 at 18:41

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