I have been working on a project of a 4-layer PCB.
Every time I add a via in order to connect two pins, another trace breaks and changes its positon.
I've added pictures to explain what I got on mind.
What's going on and how can I fix it?
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\$\begingroup\$ Looks like some automatic design rule check feature that decides to automatically reroute when you contravene a design clearance rule. \$\endgroup\$ – Andy aka May 19 '20 at 9:35
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The via requires a certain clearance to the other nets. The configuration can be changed in the constraint manager.
In the options menu, Bubble is set to shove preferred, meaning, that when routing an placing vias other traces that are in conflict with the contraints will be moved a little to avoid design rule violations.
You can adjust your design rules in the contraint manager or set Bubble to off.
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1\$\begingroup\$ +1. But setting Bubble to Off will mean you have to move the other traces by hand to clear the DRC violations. \$\endgroup\$ – user_1818839 May 19 '20 at 12:22
