I'm developing an isolated push-pull SMPS. I am attempting to transfer power through a custom center-tapped (on both primary and secondary side) transformer, stepping down from 20 V to 4 V. I am trying to cap the voltage on the secondary side at 4 V, and have been trying to do so by using turns ratio alone (5:1).
What I'm noticing, however, is my open-circuit voltage ends up being higher than what it should be given the turns ratio (for example, even after modifying turns ratio to 10:1, I would often see steady-state voltages in excess of 7 V when I'd expect ~2 V).
As I start adding resistive load, secondary voltage starts to pull down to the turns ratio, so it seems to have some dependence on current flow or lack thereof on the secondary side. What's going on here, and how do I fix it?
My best guess is maybe this is related to stray inter-winding capacitances and/or secondary leakage inductance but a) that's just a guess, and b) I don't know what to do about either in this case.
I have some sensitive devices on the secondary side that cannot tolerate more than the 4 V I'm trying to limit to, even at low- to no-current. I also cannot employ a linear regulator or zener diode on the secondary side to cap things at 4 V (maybe to eat brief voltage spikes, but not as a continuous regulator) - the short reason why is I'm fairly intolerant of losses, especially dissipative losses on the secondary side.
Update: attached a basic schematic of the architecture. I'm not, nor can I, use feedback in this application.
image source: CET Technology - Push Pull Switching Transformer Design
Specific parts are:
Controller: UCC38083
FETs: IRFZ2N4PBF
Transformer:
Diodes: 15SQ045
Output Inductor: 1 uH