An I2C device will silently ignore everything that happens on the bus until it sees a falling edge on SDA while SCK is high, followed by eight low-high-low cycles of SCK during which SDA never changes while SCK is high, and where SDA switches state on certain transitions while SCK is low. Therefore, an I2C device may safely share a bus with devices using some other protocl if the above sequence of events can be guaranteed never to occur except when trying to talk to the I2C device.
It would be possible (and not at all difficult) to have a "bit-bang" software SPI implementation ensure that the above sequence of events never occurs. Hardware SPI implementations, however, will often not allow for such a guarantee. Typically, the data output will by design change either at the same time as the clock rises, or at the same time as the clock falls. If the data wire were consistently to change state after the rising edge of the clock wire or before the falling edge thereof, there would be no possibility of SPI data being mistaken for an I2C start and addressing sequence. If the signals change at the same time, however, it would be possible that an I2C device might see some transitions happening before the clock edge and some happening after, in such a way as to be interpreted as an I2C address sequence.