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enter image description here Can somebody please tell me why do we have those tiny random spikes on the output signal? And why does the input wave behave like in the picture when we reduce the frequency of the noise source to 1kHz?enter image description hereenter image description here

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  • \$\begingroup\$ The mosfets do not conduct until V_GS exceeds the threshold, which is a rather "loose" value. I.e. for Q3 it's specified as 2.0V maximum but in reality might be smaller (1.5V or even less). I did not look up the value for Q4. So if Vnoise goes to +1.5V, and Vin is 0V, it may be possible that Q3 conducts a little. Same for Q4. If you are only simulating this, you should look into what Vth is used for each. Also, there can be considerable capacitance from gate to drain (and source) and your output is unloaded and 100kHz is pretty high in frequency. \$\endgroup\$ – Atomique May 20 at 0:53
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Part 1:

The "tiny random spikes on the output signal" in the red oscilloscope trace are noise from the circuit (at test point "IN") that provides the input to the FET gates in your CMOS inverter. IN is equal to Vin (principal square wave) plus Vnoise (100 kHz sine wave). The square wave varies from 0V to 5V. The 1.5V peak noise is added to this, producing a square wave that varies from 0V +/- 1.5V to 5V +/- 1.5V. The Gate-Source voltage (VGS) determines whether either the p-channel or n-channel FET will turn "on," either pulling the signal "OUT" up or down. The noise level is not sufficiently close to the threshold Gate-Source voltages to interfere, so a clean, inverted (NOT) output (blue trace) is produced. As mentioned by Atomique, the +/- 1.5V is close to typical or maximum VGS thresholds, so there might be a little conduction in reality.

Part 2:

In the case of the low frequency (1 kHz) noise source, your square wave is riding on a low frequency sine wave that, from the oscilloscope trace, appears to have about a 2V range. In this case, when a minimum of the square wave (0V) concides with the maximum of the sine wave (2V), you have a missing square wave where the n-channel FET (Q3) does not turn off because VGS stays above its maximum threshold value spec.

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  • \$\begingroup\$ The red signal is the input of the NOT gate and the blue is the output signal. \$\endgroup\$ – Qwerty99 May 20 at 1:45
  • \$\begingroup\$ Right. You have a 100kHz noise signal riding on your square wave. The input goes to the gates of the FETs. Because the noise level is not so large that the noise overlaps with the FET gate voltage thresholds, you get the clean inverted (blue) square wave out. \$\endgroup\$ – BalooRM May 20 at 1:49
  • \$\begingroup\$ The IN signal is the sum of V<sub>IN</sub> and V<sub>Noise</sub>. This illustrates how digital signals can reduce the impact of noise when sending signals. \$\endgroup\$ – BalooRM May 20 at 1:52
  • \$\begingroup\$ Does this make sense? We can look at the second part of your question if it does. \$\endgroup\$ – BalooRM May 20 at 1:54
  • \$\begingroup\$ Yeah it does make sense \$\endgroup\$ – Qwerty99 May 20 at 9:10

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