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I recently saw that the input parasitic capacitance of a MOSFET (Cgs, etc.) changes with the applied gate source voltage? Why is that?

I always thought that it was fixed since the parasitic capacitances are due to overlap capacitances or due to the gate channel (with oxide as dielectric) capacitor itself?

How can a physical overlap area or channel area (hence capacitance) change with the applied voltage???

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    \$\begingroup\$ There's a lot of junk going on the "plate" on the channel-side of the capacitor. It's not just a normal conductor. electronics.stackexchange.com/questions/66660/… \$\endgroup\$
    – DKNguyen
    May 20 '20 at 4:58
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    \$\begingroup\$ In outline : remember that gate voltage affects the conductivity of the channel ... when it's conducting, there is much more conductive material close to the gate. So you have moved the two plates of the capacitor closer together... \$\endgroup\$ May 20 '20 at 7:31
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the spacing of the gate "plates" will vary from

  • gate-oxide thickness

to

  • gate-oxide thickness plus depth-of-channel-bulk thickness
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