Does the PLL circuit which is used to increase frequency N times increase also the phase?

Question

If we have a PLL with the following function:

The output freq. becomes N times the input freq.

But how about the phase difference between the input and the output?

Answer 1

You have to be careful what you mean by phase, which always has to be measured with respect to something.

However, given that phase is the time integral of frequency, multiplying the frequency by N will also multiply the phase.

This means if there's a phase shift to the reference frequency, the output frequency will shift by N times that amount. If there's phase jitter on the input signal, there will be N times that amount on the output, if the jitter frequency is within the loop bandwidth.

Answer 2

This is a rich topic.

Consider a divide-by-100 counter; only ONE input edge of the 2 * 100 edges will cause the positive-going edge; ditto for the negative-going output edge.

A frequency divider preserves the statistics (the jitter) of the input edges, plus adds jitter from all those internal gates and flipflops that happen to pass along that one input edge. Plus effect of any VDD TRASH into your logic that has ZERO dB power supply rejection.

Current Mode Logic, such as the PECL family from ONNN SEMI (old MOT), has well under a picosecond of jitter contributed by each gate/ff.

Using such logic in a divider, you will find the reference time-wander to be replicated in the VCO, if the loop bandwidth permits (as Neil explained).

Answer 3

Commonly used phase detectors (such as the EXOR function) are at there "neutral point" when the difference between the divided-down-VCO frequency and the reference frequency are ±90° apart: -

The phase detector output shown above is the average DC voltage of the output meaning that when the phase difference is \$±\pi/2\$ or ±90°, the output waveform has an average value of the midpoint between the power rails. I'm referring to this as the "neutral point".

If the phase difference is not ±90°, the EXOR output waveform becomes biased towards being more positive or more negative (on average). This average signal drives the VCO in the "right" direction to acquire lock.

Any difference from the neutral point is a phase error and this is driven out by gain and integration pushing the VCO to be locked-into the correct multiple frequency. But there still might be a phase alignment error of a few degrees. This error is needed to drive the system into frequency lock.

This alignment error is relative to the reference frequency so, in terms of the VCO output frequency, the error becomes multiplied by the frequency divider step-down ratio.