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What is the difference between these features on STM32G0 "Scan Conversion mode" and "Continuous conversion mode" and "DMA continuous request" features? When you go on CubeIDE you will see these features on ADC configuration. enter image description here

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  • \$\begingroup\$ Have you read the reference manual part on the ADC? It should cover those questions quite well. \$\endgroup\$
    – Arsenal
    Commented May 20, 2020 at 11:18
  • \$\begingroup\$ @Arsenal There is no information about DMA Continuous Request on the reference manual. \$\endgroup\$
    – SalPaz
    Commented May 20, 2020 at 12:24

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I haven't checked the output of the CubeIDE if you select that option, but I think that they are referring to the feature which is described on page 325 of the reference manual (Section 14.5.5 Managing converted data using the DMA.

Basically the ADC can run in two different modes when coupled to the DMA. It can run in a one shot mode, which will stop the ADC as soon as all transfers which were configured in the DMA are finished. So you set the DMA transfer count to 10 and the ADC will stop after 10 samples during the 11th conversion.

DMA one shot mode (DMACFG=0)

In this mode, the ADC generates a DMA transfer request each time a new conversion data word is available and stops generating DMA requests once the DMA has reached the last DMA transfer (when a DMA_EOT interrupt occurs, see Section 9: Direct memory access controller (DMA) on page 241) even if a conversion has been started again.

The second mode is the circular mode. In this mode the ADC will continuously generate DMA request even if the last DMA transfer is done. This is because you can setup the DMA to work in a circular way resetting to the first position after the last transfer and start again automatically. This generates a ring buffer of continuously updating ADC samples.

DMA circular mode (DMACFG=1)

In this mode, the ADC generates a DMA transfer request each time a new conversion data word is available in the data register, even if the DMA has reached the last DMA transfer. This allows the DMA to be configured in circular mode to handle a continuous analog input data stream.

The corresponding DMACFG bit is located in the ADC_CFGR1 register.

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