1
\$\begingroup\$

I'm trying to design a 4-bit ALU which does the following functions:

enter image description here

I've written the below Verilog code and the simulation is working fine without any errors.

`timescale 1ns / 1ps

module alu_4_bit(
    
    input M,
    input S1,
     input S0,
     input C0,
    input [3:0] A,
    input [3:0] B,
    output reg[3:0] F,
    output reg Cout
    );

reg Cout_temp; // Internal Variable //

always @(*)

    begin 


                        case({M,S1,S0,C0})
                            
                            /* Logical Operations */
                            
                            4'b0000,4'b0001,4'b000x : assign F = A & B;
                            4'b0010,4'b0011,4'b001x : assign F = A | B;
                            4'b0100,4'b0101,4'b010x : assign F = A ^ B;
                            4'b0110,4'b0111,4'b011x : assign F = ~(A ^ B);
                            
                            /*Arithmetic Operations*/
                            
                            4'b1000 : assign {Cout,F} = {4'b000,A};
                            4'b1001 : assign {Cout,F} = A+1;
                            4'b1010 : assign {Cout,F} = A+B;
                            4'b1011 : assign {Cout,F} = A+B+1;
                            
            /* When there's negation of any one data entry, Cout also gets negated */
                            
                            4'b1101 : 
                            begin
                            assign {Cout_temp,F} = A+(~B)+1;
                            assign Cout = ~ Cout_temp;
                            end

                            
                            4'b1111 : 
                            begin
                            assign {Cout_temp,F} = (~A)+B+1;
                            assign Cout = ~ Cout_temp;
                            end
                            
                            
                            4'b1100 : 
                            begin
                            assign {Cout_temp,F} = A+(~B);
                            assign Cout = ~ Cout_temp;
                            end
                            
                            4'b1110 :
                            begin                           
                            assign {Cout_temp,F} = (~A)+B;
                            assign Cout = ~ Cout_temp;
                            end


                            default : assign {Cout,F} = 5'b00000;
                            
                        endcase 
                    
    end

endmodule

But when I'm trying to synthesize the project and View the Technology/RTL Schematics, I'm encountering the following error:

enter image description here

Can anyone point out where the mistake is and help me rectify it?

\$\endgroup\$
2
  • 5
    \$\begingroup\$ In the always @(*) block, you don't need the assign key word, the comb logic is implied. \$\endgroup\$
    – awjlogan
    May 21 '20 at 10:40
  • 1
    \$\begingroup\$ Yes, this helped me in successfully generating the synthesis file. \$\endgroup\$ May 21 '20 at 11:24

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Browse other questions tagged or ask your own question.