# ΔΣ ADC Programmable Gain Without Amplifier

There are some ΔΣ ADCs of which one can set an input referred gain. Like if there was a PGA between the input and the ADC, but in fact, there seems to be no PGA between the ADC and the inputs but instead the gain is set inside of the ΔΣ modulator somehow.

For example this one form Analog Devices: https://www.analog.com/media/en/technical-documentation/data-sheets/2480fe.pdf

Am I right, that there is no amplifier between the input and the ADC here and the gain is set somehow in the modulator? How is that even possible, setting the gain in the ΔΣ modulator.

I am interested in this, because, if I am reading the datasheets correctly, there will be an input current I need to account for even though if I set a gain to the ADC, since there is no amplifier on the input. But, if I am wrong, then the amplifier should provide a high Z input and decreased input current.

• Don't see how you can do it in the modulator, but it's trivial to do in the decimation filter. And the linked device does have a buil-in decimation filter.
– user16324
Commented May 21, 2020 at 11:49
• @BrianDrummond If you do it in the decimation filter, does that increase the input referred resolution? I'm not very familiar with the mathematics of it... Because tables 2a and 2b clearly says that buy increasing the gain you increase the resolution so it can't be a simple digital multiplication. But maybe you average more samples and get a higher resolution like that? But than why does the input dynamic range decrease with the higher gain? Commented May 21, 2020 at 12:34

Don't see how you can do it in the modulator, but it's trivial to do in the decimation filter. And the linked device does have a buil-in decimation filter.

If you do it in the decimation filter, does that increase the input referred resolution? I'm not very familiar with the mathematics of it... Because tables 2a and 2b clearly says that buy increasing the gain you increase the resolution so it can't be a simple digital multiplication. But maybe you average more samples and get a higher resolution like that? But than why does the input dynamic range decrease with the higher gain?

I think you answered the question yourself in this comment...

Digital filters tend to involve word growth : if you multiply two N-bit numbers the product is effectively either 2N or 2N-1 bits. (For signed data, 2N-1 bits is the practical result because multiplying 2 sign bits produces ... 1 sign bit)

The decimation filter (following the delta-sigma modulator) is generally an FIR filter. which involves multiplying some large number like 100 samples with 100 coefficients, and summing all the results.

If the samples from the modulator and the coefficients are each 16 bits, and you sum 2^7 samples, the result is thus a (31 + 7) = 38 bit quantity.

Now you need to extract a 16 bit result from this...

Word format (s = sign, d = useful data, n = noise) of the filter output...

37 ...  31 ....   23 ...    15 ...    7 ...   0
ss_sddd_dddd_dddd_dddd_dddd_dddd_ddnn_nnnn_nnnn
| low gain setting     |
Above  is a typical filter output for a large amplitude input

ss_ssss_ssss_sddd_dddd_dddd_dddd_ddnn_nnnn_nnnn
| high gain setting    |
And for a low amplitude input


The "programmable amplifier" is simply a selector, choosing 16 of the (in this case) 38 filter output bits. The gain steps are constrained to be powers of 2.

By selecting lower order bits for the higher gain setting, naturally large input signals will overflow (thus dynamic range is reduced) but the last couple of bits contain noise, as shown in Table 2A.

This is just an illustrative example : the details of your device will vary but it is highly likely to follow this principle. The lower order bits (7 downto 0 here) will simply never be calculated, to save logic. And there may be saturation logic so that any positive overflow saturates at + full scale instead of wrapping to a spurious -ve output (and vice versa).

Reading the data sheet, this device apparently uses a much simpler Sinc4 filter instead of the FIR filter I described above (common in more critical applications like audio) but the principle is similar.

I have shown the top couple of bits unused : DSM performance usually degrades catastrophically near the top of the input range where the "noise" from noise shaping and the input signal sum to an out-of-range value. Simply ignoring the top bit or two is an easy way to achieve this. Quoting the datasheet for this device:

" The proprietary architecture used for the LTC2480 third order modulator resolves this problem and guarantees a predictable stable behavior at input signal levels of up to 150% of full-scale. "

but in fact, there seems to be no PGA between the ADC and the inputs but instead the gain is set inside of the ΔΣ modulator somehow.

Well, the block diagram doesn't imply it's inside the ΔΣ modulator. It implies it is inside a block labelled 3rd order ΔΣ ADC i.e. it doesn't mention the word modulator. Of course there may be somewhere else in the data sheet that does say this but it's not said that way in the block diagram so, just regard it like this: -

• On page 28 it says that "The input and reference pins of the LTC2480 converter are directly connected to a network of sampling capacitors. Depending upon the relation between the differential input voltage and the differential reference voltage, these capacitors are switching between these four pins transferring small amounts of charge in the process." This, too me, strongly implies that there is no PGA like on your drawing but instead the front end of the modulator is directly connected. But, is that true for gain 1 only and they just don't say it and a PGA is used for higher gains? Commented May 21, 2020 at 12:26
• Or they somehow integrated the gain into the modulator which would make the analog input specs valid for all gains? Is that possible? How? Commented May 21, 2020 at 12:27
• Personally, I don't care how they implemented it providing that the data sheet gives me enough information to use it. If it doesn't AND I think it's a good device to use I dig around until I get an answer and, if necessary contact Linear Tech (or whoever) to get that answer. In the absence of a definite answer, I move on to look at other chip/supplier options. Commented May 21, 2020 at 12:45

The datasheet goes into considerable detail regarding the analog inputs starting on page 28. I'm not sure why you think that the gain setting would have any effect on this, since they never mention it.

The gain errors are very tiny, so it's easy to believe that the variable gain is a digital function within the convertor, not a separate amplifier.

• The gain error is small because it calibrates it continuously. I did read through the analog input sections, and that is exactly what confused me, because it says that the inputs are connected directly to the sampling caps. But maybe it is only true for a gain of 1 and they just don't explicitly say that because they think it is trivial? That is why I am asking; Is it possible to integrate the gain into the modulator? If you look at tables 2a and 2b, you can see that by increasing the gain you increase the resolution, so the gain can't be all implemented in the digital domain. Commented May 21, 2020 at 12:19
• Why do you insist on saying that? For example, reducing the reference voltage would reduce the full-scale range, effectively increasing the gain. Similarly, reducing the sampling time in the switched-capacitor blocks effectively reduces the gain. None of this affects the input characteristics. They could be doing any combinations of these things, or something completely different. Unless we can talk to the chip designer, we'll simply never know. Commented May 21, 2020 at 12:51