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I am trying to understand switching behaviour of PMOS transistor and how exactly it passes a bad 0 value. I'm getting confused with the notation.

More specifically, when the PMOS is on and \$V_{in}=0\,\textrm{V}\$, why does \$ V_{out} = V_{DD} - |V_{tp}| \$?

For NMOS, I apply the equations as following when the NMOS is on and the input is high, $$ V_{gs(min)} = V_{tn} = V_{DD} - V_{out}$$ which implies: $$ V_{out(max)} = V_{dd} - V_{tn} $$ For PMOS however, I have: $$ V_{gs(max)} = V_{tp} $$ Now when I rewrite LHS as: $$ V_g - V_{s(min)} = V_{tp} $$ Since \$ V_g = 0 \$, I get this weird result for \$ V_s \$.

How do I relate \$ V_s \$ to the output?

Video link for reference: https://youtu.be/z2yqmHClVO8?list=PLB3F0FC99B5D89571&t=1457

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    \$\begingroup\$ Hit the edit link and add the URL for the video in case anyone wants to get the context. \$\endgroup\$
    – Transistor
    Commented May 21, 2020 at 12:38
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    \$\begingroup\$ Do you understand how an NMOS operates as a switch? \$\endgroup\$
    – Andy aka
    Commented May 21, 2020 at 12:39
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    \$\begingroup\$ @Andyaka Yes, and I am able to derive it myself too. I just don't seem to get it for PMOS. When I apply the PMOS equations myself, I get a different result. \$\endgroup\$ Commented May 21, 2020 at 12:40
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    \$\begingroup\$ So, show your NMOS derivations in your question and explain that you can't seem to be able to repeat for PMOS. \$\endgroup\$
    – Andy aka
    Commented May 21, 2020 at 12:46
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    \$\begingroup\$ @Andyaka Edited.. \$\endgroup\$ Commented May 21, 2020 at 13:02

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If you want to understand why PMOS passes a bad 0 value, take a look at the circuit below:

schematic

simulate this circuit – Schematic created using CircuitLab

If we assume \$ V_{in} = 0\,\textrm{V} \$ and \$ V_{DD} = 0\,\textrm{V} \$ and the capacitor has an initial voltage of \$ 5\;\textrm{V} \$:

The pin connected to the capacitor is effectively the source, because it has the higher voltage, therefore drain is the pin connected to \$ V_{DD} \$.

Let's also assume that \$ V_{tp} = -1\,\textrm{V} \$. Because, $$ V_{S} - V_{G} > |V_{tp}| $$ the PMOS is turned ON and there is a path for the capacitor to discharge.

This continues until the capacitor's voltage reaches \$ |V_{tp}| \$, where conduction slows and eventually ceases.

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  • \$\begingroup\$ This answer is confusing me. If the capacitor is at 5V, the body diode of the PMOS device would be forward biased, and the capacitor would quickly discharge with high current until it goes below about 0.7V. And the capacitor is connected to the DRAIN of M1, so it should not be called SOURCE. \$\endgroup\$
    – PStechPaul
    Commented Jul 31, 2022 at 4:01

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