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Why does the simulator calculate different results for these signals: prova1 and prova2? In my opinion, those are representing the very same function.

Signal declaration is:

logic [12:0] sub_ton;
logic [11:0] sub_ton_neg;
logic prova1;
logic prova2;

enter image description here

Here are simulation results: enter image description here

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  • \$\begingroup\$ Please can you add sub_ton to your waveform and how it's driven. And also expand the wave around the relevant part so sub_ton_neg is fully visible :) \$\endgroup\$
    – awjlogan
    May 22, 2020 at 14:42

1 Answer 1

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Your problem is the rules for Verilog expression bit length say that operands get extended to their context determined lengths before applying the operators. In the expression:

~(sub_ton[11:0])+1

The +1 is really +32'sd1, a signed 32 bit decimal number. sub_ton[11:0] gets 0-padded to 32 bits, then the bitwise negation happens, followed by the addition. When you make the assignment to sub_ton_neg it gets truncated back to 12 bits. That truncation doesn't happen in your 3rd assignment to prova2.

This little example should give you a better picture of what's happening.

module top;
  bit [12:0] sub_ton=1;
  bit [11:0] sub_ton_neg;

  initial begin
    sub_ton_neg = (~(sub_ton[11:0])+1);
    $displayh(sub_ton_neg);
    $displayh((~(sub_ton[11:0])+1));
  end
endmodule

The rules are explained section 11.8.2 Steps for evaluating an expression in the IEEE SystemVerilog 1800-2017 LRM. These rules have been in place since before the IEEE Verilog 1364-1995 LRM.

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