# Differential amplifier (transistors): Which input is inverting?

For example, on the following differential amplifier it is clear, which of the inputs is the inverting one. If the voltage on the non-inverting input (base of Q1) is higher, the current through Q1 will increase. That leads to a higher voltage on R2 and the collector potential will go down. On comparison, the current through Q2 is being decreased which means less voltage through R4 and the collector (=output) will become higher. Is that correct?

However, on this circuit, it looks different: The inputs are swapped as the output is being taken from the "non-inverting transistor". However, logically the output should become lower when increasing the positive input? I don't understand how they come to the conclusion that the inputs are correct?

simulate this circuit – Schematic created using CircuitLab

• What does that last transistor (driving the output) do....? Commented May 22, 2020 at 15:04
• Please label your transistors with designators. If I tell you something about "the 3rd transistor" do you know which one I mean? Commented May 22, 2020 at 15:04
• I just found the circuit on an forum and was wondering why the inputs are like that as I would have swapped them (from my logic). The circuit is a very simple form of an opamp (differential amplifier + driving the output like you said). I also think the last transistor does some voltage amplification as well. I'm sorry for the missing labels but I just copied the circuit from another website. Commented May 22, 2020 at 15:09
• I have redrawn your second circuit to give it references using the tool on this site. Without these its difficult to discuss how the circuit operates. Please ensure we have these on any other circuits you post. Commented May 22, 2020 at 15:28

$$\Q_4\$$, $$\D_1\$$, $$\D_2\$$, $$\R_2\$$ and $$\R_4\$$ form a constant current sink.

Increasing the voltage on the base of $$\Q_2\$$ causes the voltage at its collector to fall. This in turn turns $$\Q_3\$$ on more increasing the output voltage.

So clearly $$\Q_1\$$ base is the inverting input, $$\Q_2\$$ base is the non-inverting input and $$\Q_3\$$ collector is the output.

The PNP transistor is in common-emitter configuration. The CE stage inverts its input.

Therefore the signal that was inverted at the output of the differential stage is inverted again at the final output, meaning it's not inverted compared to the original input.

• Thank you! Would it make a difference if the last transistor was an NPN one? Commented May 22, 2020 at 15:11
• @Waln3, yes, if the last transistor was NPN, then you'd have a CC stage as the second stage, which doesn't invert its signal. Commented May 22, 2020 at 15:15

opposite inputs and output will be in phase.