1
\$\begingroup\$

Can I "break" an always blocks in Verilog? I would like to rewrite

  always @(posedge clk_i or posedge rst_i) begin
    if(rst_i) begin
      // Do stuff
    end else begin
      // Do stuff
    end
  end

as follows (which I find cleaner):

  always @(posedge clk_i or posedge rst_i) begin
    if(rst_i) begin
      // Do stuff
      break;
    end

    // Do stuff
  end
\$\endgroup\$
  • \$\begingroup\$ This seems dangerously close to forgetting that the operations described are not executed sequentially as in a software programming language, but rather in parallel. \$\endgroup\$ – Chris Stratton Nov 29 '12 at 15:31
4
\$\begingroup\$

Yes, you should name your begin-end block and then use disable statement like this:

always @(posedge clk_i or posedge rst_i) begin : block_to_disable
  if(rst_i) begin
    // Do stuff
    disable block_to_disable;
  end

  // Do stuff
end

Though, this is probably non-synthesizable, so you can do such tricks only in simulation (testbenches, etc.).

\$\endgroup\$
  • \$\begingroup\$ I'd feel that if the compiler made a bit of an effort, this could be synthesizable. \$\endgroup\$ – Randomblue Nov 29 '12 at 14:05
  • \$\begingroup\$ @Randomblue - you'd be better off learning to think in terms of hardware operation, than expecting the tools to synthesize from software paradigms. Remember these are not sequential operations - everything happens at the same time. \$\endgroup\$ – Chris Stratton Nov 29 '12 at 15:30
  • \$\begingroup\$ I understand that. But there is the rule that when multiple assignments to the same register are done, the last one wins. There is no ambiguity. So the compiler just has to figure out the last assignment for every possible combination of the input signals. \$\endgroup\$ – Randomblue Nov 29 '12 at 15:32

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.