I need to buffer 1.5Gb/s of video data through SDRAM, which works out to be 3Gb/s total in and out combined.
This is my thinking so far:
Write/read burst length is set to max (16 clock cycles), and CL is 3 clock cycles, that means for every 16 clocks, I need at min another 3. So 19% overhead for just CL between bursts.
Changing banks/rows is another 15 clock cycles (RP + WR + RC). The max number of burst writes I can make without changing rows is 64 (according to the Xilinx spartan 6 MCB user guide page 17). This takes 77 clocks (64 writes of 16 bits * 1.19 for CL overhead) and requires an additional 15 clocks for config (or 20%) between rows.
3Gb/s * 1.19 * 1.20 = 4.28 Gb/s.
I'm considering clocking a LPDDR device at 166Mhz, which gives 332Mhz for both clock edges. If I use a device with a 16 bit word length, i get
332Mhz * 16 bit = 5.3 Gb/s, within my spec quite comfortably.
Perhaps this device?
My main question is: Am I on the right track here? This is the first time I've had to design a board containing SDRAM, do these numbers look right? Is there any way I can configure the chip to further minimize the overhead? Is there anything else I need to consider? The last thing I want is to select a device, build the board and then discover that my choice is too small/slow for my application.