Simple version of an internal op-amp circuit

Question

I'm currently learning how op-amps and transistor circuits work and want to understand the simple version of an internal op-amp circuit. However, there are still some open questions.

The first stage here is a differential amplifier with R3 as the constant current sink. There may also be a transistor current sink or current mirror when I'm not wrong. T3 is a level-shifter (common-emitter, voltage-amplification). It receives a small current from the collector of T1, which is proportional to the input difference (U_pos minus U_neg), right? That means T3 creates an inverted voltage on its collector (output), which is proportional to that current. (I'm not exactly sure as T3 may also use the voltage from T1 collector?). However, why not using an NPN transistor? T4 is a common collector circuit that provides a small output resistance and amplifies the current (power-amplification).

Is my understanding correct?

The resistors I have used to simulate are not proper as the output gets into the negative saturation when I insert a small AC signal on the pos. Input. How can I calculate the resistors so that the output has a good range between Ub+ and Ub-? How can this circuit be improved (I'm aware of adding a better constant current sink made of a transistor)? I also saw some capacitors sometimes, would that help? Maybe a capacitor in front of T3 to remove offset?

Thank you!

Answer 1

The following answer concerns the principle operation only. That means, I do not speak about resistor values and alternatives to optimize the circuit.

• As you have mentioned - T3 acts as a "level shifter" (with amplification). For this purpose, T3 must be a pnp type. Otherwise, the DC quiescent collector potential of T3 could not be lower than the potential at the T1 collecor. But this is necessary because of the desired DC output voltage of 0 V.

• Quote: "...T3 creates an inverted voltage on its collector (output), which is proportional to that current. (I'm not exactly sure as T3 may also use the voltage from T1 collector?)...."

  This point touches the general question if the BJT is to be considered as a current-controlled or a voltage-controlled device. In this circuit, and for calculation purposes, this question is not too important - both models can be used. However, if the current gains of the transistors are not known, the voltage-control model is to be preferred (using the transconductance gm=Ic/Vt).

UPDATE: I have roughly calculated the overall gain (using your resistor values and assuming a beta=200). The current through R3 is app I3=125µamp and the current through R4 is app. I4=2mA. The gain of the first stage at the base of T3 (with consideration of the input resistance at the base of T3) is app. A1=-65 and the gain of T3 is app. A3=-2. Hence, the overall gain is app. A=+130.

Answer 2

Your reasoning is correct except for the amplifying stage implemented with T3. It is a voltage amplifier driven by the voltage drop across R1. This stage can be considered as two cascaded sub-stages - an active voltage-to-current converter (consisting of T3 and R4) and passive current-to-voltage converter (the resistor R5). Note that its output voltage is the voltage drop across R5.

So, your assumption "I'm not exactly sure as T3 may also use the voltage from T1 collector?" is somewhat true.

To calculate the resistance values ​​and improve the circuit, you have to have a good idea of ​​how it works in common, differential and single-ended mode (the latter is shown in your picture). Is that so?

Answer 3

I like this circuit; shows several useful principles of transistors.

For a wider output range(top end), reduce the values of R1, R2, R4 by 50%. Try 36k, 36k, and 1k.

If you reduce these 3 resistors by 75%, to 18k, 18k and 510 ohm, you'll improve a bit more.

For better offset voltage (that is, to keep the Vout nearer zero volts when the Vin is zero), I'd add a diode in series with R1, diode_bar down; this is to compensate for the base_emitter voltage of Q3.

Your gain will be the product of:

• R1 / (reac_Q1 + reac_Q2) == 75,000 / (500 + 500) == 75X

• R5/R4 == 4,000 / 1,000 == 4X

where reac_Q1 and reac_Q2 == [ 0.026 volts / emitter_current_amperes ], and the "reac" is the linearized small_signal calculus_derivative of the diode equation of the base_emitter behavior of the 2 transistors of your diffpair.

At 1 mA (tail current would be 2 mA thus R3 is 4.3 kohm) thru each of the diffpair devices, their reac is 26 ohm for a total of 52 ohm; the gain of that first stage would be 75,000 / 52 = 1,400X. This is good, except the voltage required for R1 would be 75 VOLTS and your rail is 10 volts.

Thus you might replace R1 with a 1 mA PNP current source.

To better evaluate your present circuit, inject +- 1 millivolt.

To remove some/most of the DC offset, do this:

• diode in series with R1

• diode in series with R5

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The computed gain is with 'reac' of 500 ohm in each emitter of the diffpair, with 50 uA in each emitter, thus 75k as the tail resistor.