I have some old Altera MAX EPM7128SLC84-15N CPLDs kicking around that I want to use to interface with 5v TTL logic.

Device pinout

If you look at the pinout, some of the pins have more than one function (eg. Pin 2 can be an input, output enable or global clock). How do you select which one it is and which one is it by default?

In Quartus II (I'm using version 13.0.1 Web Edition 32-bit), if I go to assignments -> device -> device and pin options everything is greyed out. Everything is greyed out in configuration as well. The only configuration scheme I get is "n/a in MAX7000S".

Dual use pin options

By the way, I'm aware that this is an obsolete part and there are modern 3.3V CMOS CPLDs that are compatible with 5V TTL logic. I have these parts in hand and would like to use them if at all possible.

  • \$\begingroup\$ The software should have some type of pin planning tool so depending on the layout of your board, you will have to choose a pin that will correspond to your desired input and output devices. Intel has a guide for first time programming. While this is an FGPA guide, it does show you how to use the Quartus software. \$\endgroup\$
    – user103380
    May 24, 2020 at 16:19
  • \$\begingroup\$ It does have a pin planner but it only allows you to choose which signals go to which pins, it doesn't seem to have an option to configure the dual use pins. \$\endgroup\$
    – santonel
    May 24, 2020 at 17:10

1 Answer 1


The functionality of the pins is inferred from your code, rather than set directly. The pin names are telling you what that pin could be connected to internally within the FPGA.

enter image description here

The above diagram shows what INPUT/OE2/GLCK could be connected to. Note that while it looks like it's connected to everything at once, that is not the case.

To connect to the GCLK2 network you need to infer a clock by using the signal from that pin to drive the clock input of a register. Don't forget your timing constraints for this. To connect to the OE2 network use the signal to control the output enable on an IO block by either instantiating an IOB megafunction or writing the right code pattern to infer an IOB. To connect to the general purpose interconnect just feed to a logic block as normal.

For fun you could connect to all three and watch the synthesis tools have a fit as they try to decide what it is you want to do.


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