Timing specifications in a communication protocol

I am having this I2C EEPROM Chip from Onsemi - CAT24C

In table 6, AC Characteristics of the datasheet, only the Minimum time is provided for the SCL clock low and high period.

My questions :

1. Not only with this IC, in some Microcontrollers too, I have observed this scenario. In the timing characteristics of the IC / Microcontroller, why are the manufacturers providing only the Minimum (or in some cases maximum alone) values?

2. On what parameters (internal logic like TTL, CMOS?) do these timings (For example, setup time, hold time, rise time and fall time) depend upon? Like, why do they provide only either Minimum or Maximum but not the range of values within Minimum to Maximum? What is the reason behind it?

• 1) because sometimes there is no maximum. You can set SCL high tomorrow if you like, and low again on Wednesday, and the comms will still work (battery life permitting). 2) Design dependent, which is why every design needs its own datasheet. – Brian Drummond May 25 at 9:52

The two most common speeds in I2C are 100kHz (standard) and 400kHz (fast). There are higher speeds in the specification but these are the two most commonly used.

It is not necessary to actually use those speeds; in normal mode there is no reason that we could not use a 50kHz clock (100kHz is the maximum speed in normal mode and for this reason it is usually stated that this can run at rates up to 100kHz).

It is also important to note that I2C is specified down to DC so there will not be a maximum time.

If we look at the clock rates for each, we find that at 100kHz the clock period is $$\10 \mu S\$$ and the values shown mean that the minimum duty cycle is 40% and the maximum duty cycle is 53% (a little unusual as 45 / 55 is very common but this is what the manufacturer is stating as guaranteed to operate).

At 400kHz, the clock period is $$\2.5 \mu S\$$ and the minimum timings show that a duty cycle of between 24% and 52% is required at 400kHz.

For whatever reason, a high duty cycle would interfere with operation (I have no idea why) at the maximum available rates.

For logic, input setup time is specified as the minimum required for guaranteed operation; the signal timing cannot be less than this, but could be more by any value so the maximum is irrelevant. Looking at the diagram, if the data were available earlier, the setup time is still met.

Hold time (the amount of time an output is maintained in the given state after an event - usually a clock or an input must be maintained after a clock) is specified as the maximum amount of time the output will still be stable; any shorter time will still have the output stable and therefore a minimum time is irrelevant. For an input there may well be a minimum hold time, but there will be no maximum.

• Thank you for the answer. I got 2 queries from your answer. 1. "I2C is specified down to DC so there will not be a maximum time" - What do you mean by this? How can the communication happen between 2 devices when the clock frequency is 0Hz? 2. On what parameters are the setup, hold, rise and fall time dependent on? Does it depend on the internal logic of the ICs (Like CMOS or TTL)? – Newbie May 25 at 10:37

Consider this: -

I've highlighted the clock frequency in green. For the standard setting, the clock frequency can be no greater than 100 kHz but there's no reason why you can't operate it a 1 nano hertz. If operating at 1 nano hertz then the low period of the SCL clock could be as long as 500,000,000 seconds.

But who really cares because what this data sheet is telling you is that the device is capable of fully static operation down to a clock frequency of virtually zero hertz.

• Thank you. But how can the communication happen when the clock frequency is 0Hz? – Newbie May 25 at 10:30
• Basically it doesn't happen but if someone wanted to operate at a really slow clock then why should this be prevented - a static design means it is capable of working at any frequency up to the maximum specified. – Andy aka May 25 at 10:33
• Thank you for the clarification. Could you also help with the second question on "what factors / parameters do these timings depend? The internal TTL or CMOS logic? – Newbie May 25 at 10:35
• How this gate or that gate, this chip or that chip does this is IP to the manufacturer and, as EEs we have to accept what is said in the data sheet and realize that the detail design of the chip/gate will be unknown to us. – Andy aka May 25 at 10:39