The two most common speeds in I2C are 100kHz (standard) and 400kHz (fast). There are higher speeds in the specification but these are the two most commonly used.
It is not necessary to actually use those speeds; in normal mode there is no reason that we could not use a 50kHz clock (100kHz is the maximum speed in normal mode and for this reason it is usually stated that this can run at rates up to 100kHz).
It is also important to note that I2C is specified down to DC so there will not be a maximum time.
If we look at the clock rates for each, we find that at 100kHz the clock period is \$10 \mu S\$ and the values shown mean that the minimum duty cycle is 40% and the maximum duty cycle is 53% (a little unusual as 45 / 55 is very common but this is what the manufacturer is stating as guaranteed to operate).
At 400kHz, the clock period is \$2.5 \mu S\$ and the minimum timings show that a duty cycle of between 24% and 52% is required at 400kHz.
For whatever reason, a high duty cycle would interfere with operation (I have no idea why) at the maximum available rates.
For logic, input setup time is specified as the minimum required for guaranteed operation; the signal timing cannot be less than this, but could be more by any value so the maximum is irrelevant. Looking at the diagram, if the data were available earlier, the setup time is still met.
Hold time (the amount of time an output is maintained in the given state after an event - usually a clock or an input must be maintained after a clock) is specified as the maximum amount of time the output will still be stable; any shorter time will still have the output stable and therefore a minimum time is irrelevant. For an input there may well be a minimum hold time, but there will be no maximum.