# decoupling capacitors for DC-DC converters

I am using a DC to DC converter (Murata MEJ2S0505SC (datasheet)) (5 V to 5 V at 500 mA) for isolation purposes. Now I want to calculate the input decoupling capacitor.

Can anyone please suggest any methodology to calculate it? (Note: It is not mentioned in the data sheet.)

• Have you tried simulating it? – winny May 25 '20 at 11:57
• Now i added data sheet,and i did not simulated and i need theritical explanation. – yugi May 25 '20 at 12:03
• The capacitor is usually associated with an inductive element to form a front-end $LC$ filter. You dimension these components based on a maximum allowable input ripple current at a certain frequency. Usually a small $L$ is adopted as it supports the dc current while a large capacitor can cope with the high-frequency pulses absorbed by the dc-dc module. Have a look at a seminar on filters I taught at an APEC conference in 2017. The example starts slide 80. Don't forget to damp the filter. – Verbal Kint May 25 '20 at 12:12
• Did you look through their application notes, DCAN-68 "Low power isolated DC-DC application notes"? – SteveSh May 25 '20 at 12:18
• murata.com/-/media/webrenewal/products/power/appnote/… – Andy aka May 25 '20 at 12:53

The input filter specifications depend on: (1) your source impedance and (2) dynamic frequency of the DC-DC converter (3) the spectrum of your step load. (4) radiated EMI of source current and conducted noise as a result of (1,2,3)

This is a 2-way filter spec. If you require load regulation noise on the source, the unbalanced load impedance being the input to the DC-DC can generate noise on the source.

Consider the input cap. as a LPF to the source impedance including path inductance, both DM and CM. Ideally, you want 0 Ohms and expect a well-designed DC-DC converter from Murata will have dampened chokes with suitable Q's or L/R ratios.

## Design thought experiment

• Consider the voltage divider relationship of a repetitive pulse with load impedance and the ESR of your input cap
• define your allowed load ripple voltage error / step load current = Step Zout
• Consider the impedance of Cin @ f DC-DC = Zc(f)
• be aware that the C*ESR =Tau product is limited by the type and quality of capacitor material < 10us for low ESR e-cap and > 100us for G.P. e-cap. while Ceramic is lower density much much faster Tau.
• Now define Z cap in terms of minimum C and maximum ESR @ f for step load I at output ripple Vpp

To meet all the considerations in the beginning; it may end up being a CM choke with two caps in a CLC or Pi filter with a certain differential attenuation Bode Plot that is trivial to design on Falstad's Analog filter site after you define impedance and attenuation @f.

• Might also suggest using multiple caps in parallel possibly of different types, due to self-resonance and series resistance - to get filtering over a wider range of frequencies. – scorpdaddy May 25 '20 at 13:26
• Certainly @scorpdaddy,, I imagine the Zcap(C,f,+ESR) of the caps over the load spectrum must be closer to zero than any possible negative incremental resistance For the input Z(V,f) of the DC-DC in the boost startup mode in order to be stable. – Tony Stewart EE75 May 25 '20 at 19:31