# Is the current, Ids, through a MOSFET truly 0 when in the cutoff region?

I was testing a circuit using this circuit simulator and found that the nMOS transistor had a current of a few nanoamps running through it when it was in the "off" state. This was unexpected because I was taught (and found online) that the current through a MOSFET in the cutoff region was 0.

After a lot of thinking, I've decided that it seems odd that it would ever be exactly 0 since everything about a MOSFET varies in a continuous fashion. In the same way that there is no real point that the MOSFET changes from linear to saturation (as in, it does not suddenly switch to saturation as soon as , it's more of a transitional phase), it seems reasonable to assume that there is no real "off" state of a MOSFET, rather just a very low current linear region. But if that was true, surely I'd be able to find an equation which models the current in the cut-off region. I thought the linear region equation would work, but the results I get from that do not match those of the simulation.

The reason this is an issue for me is that it means the voltage output is dependent on the value of the resistor when in the off state.

It's all about $$\I_{DSS}\$$ so pick up a data sheet for a MOSFET and look up that term. It'll tell you something like: -

It's the drain current that flows when the gate and source are connected i.e. $$\V_{GS}\$$ = 0 volts. It's usually specified for a high-ish drain source voltage of maybe 10 volts to hundreds of volts.

Basically it's the leakage current of the channel.

• Thanks. I never would've guessed it was that simple. I had a look at the datasheet for 2N7000 and found $I_{DSS}$. I noticed that it varies depending on $V_{DS}$ and $T_C$. It appears the 4 measurements in the datasheet are the only information available for it. Does that mean there is no (known) equation to find $I_{DSS}$, so those values are just attained by the manufacturer testing the MOSFET? Is there any way to calculate $I_{DSS}$ for a given $V_{DS}$? – JolonB May 25 '20 at 11:57
• I'm sure there are theoretical formula for $I_{DSS}$ based on channel width and length and temperature but I've never seen much in data sheets i.e. they tell you what the max is and I've never seen typical values or formulas. It is important in some designs to know this and I've learned never to rely on MOSFETs when you want high off impedance and low leakage current. – Andy aka May 25 '20 at 12:03
• What would you use for high off impedance instead? I want a very low current, so I'm all ears if there's something better. The reason for my main question was that my actual circuit is a bit larger. Since the output voltage decreases as the input increases, I get some unexpected results because the voltage is in an undefined logic state. I've been trying to calculate the optimal resistance for minimum current draw whilst retaining correct logic levels. However, without being able to calculate the current, I'm a bit stuck. – JolonB May 25 '20 at 12:14
• I'd use an analogue switch for low leakage (circa 5 nA) if you choose the right device. You can get on-resistance down to less than an ohm but that doesn't mean an analogue switch is suitable for what you want in broader terms. – Andy aka May 25 '20 at 12:23
• Yes, I believe the 4066 isn't good for doing that. It's got 125 ohms on resistance too. No, there are better analogue switches than that. I use a few ADG1604 just as an example for switching gain setting resistors. But there are other variants. – Andy aka May 26 '20 at 7:59

At high temperatures the FETs leak a lot.

read the opamp datasheets, and notice how the +125 ° C input currents grow 100x or 1,000x.

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MOSFETs also have a subthreshold region, just below Vthreshold, where the Idd varies exponentially with gate voltage. Those implanted heart pacemakers use this phenomena.

They can manufacture MOSFET devices with threshold voltages that are (for an N-channel device) positive, near zero, or negative.

When Vgs is rather less than the threshold voltage you get kind of an unwanted leakage (or in some micropower circuits it's actually a useful operating region).

In the subthreshold (weak inversion) region the drain current is exponentially related to the gate voltage. More in this Wikipedia entry.

It is completely all right to have some $$\I_{DS}\$$ current for $$\V_{GS}=0\$$. Actually there are multiple type of MOSFET devices which conduct at $$\V_{GS}=0\$$.

"off" and "on" states are terms from the binary word of digital domain, but here you have an analog application, and thus everything continuous, and finite.

There is a doped silicon "resistance" (=channel) between the drain and the source, whose resistance can be controlled with the gate voltage. So, when $$\V_{GS}=0\$$, the resistance of the raw doped silicon is seen without any electron enticing from the gate. Because this is what happens in an enhancement MOS device: with increasing gate voltage (for nMOS), electrons will be lured to the vicinity of the gate-channel interface, and these free moving electrons can carry current between the drain and the source, thus the resistance of the channel is reduced.

The main difference between saturated and sub-threshold region is what part of the charge transport is dominant: drift or diffusion, but the above simplified description is valid in every operational region, just the effect of the gate-channel voltage is changed.

• You've completely forgotten to consider the pn junctions that exist when below the threshold voltage. They're more significant than the channel resistance in cutoff. – Hearth May 25 '20 at 14:55
• @Hearth the pn juctions are normally reverse biased. It is true though, that they have some current, but I wanted to give a general, high level answer. I feel that such a generalized and simplified model, where I neglect the reverse current of a diode fits better to OP's current understanding. – Horror Vacui May 25 '20 at 15:03
• But that reverse bias is the entire reason the current is so low in cutoff. It has nothing to do with the bulk silicon resistance. – Hearth May 25 '20 at 15:11
• I disagree. I've many times had issues with the output resistance of turned-off transistors due to their DS leakage, but barely due to the diodes. Nowadays the resistance of a transistor in any advanced nodes is not negligible even in the "cutoff" region for sensitive analog designs. With discrete implementation it might be different, but in university curriculum, the junction current is often omitted in simple explanations for simplicity. The reverse bias current is usually only an issue at very high temperatures. The OP said nothing about elevated temperatures, so I assume room temperature. – Horror Vacui May 25 '20 at 16:21
• But all of the current going through the body resistance must also go through one of those pn junctions. – Hearth May 25 '20 at 16:23