1
\$\begingroup\$

I have noticed that when I was designing universal logic gates like CMOS NOR gate that uses PMOS for pull-up and NMOS for pull-down.

Then I faced it for second time with the H-bridge circuit, but in this case the upper part of H-bridge was PNP and the lower part was NPN (I don't know if I can call it pull-up and pull-down ) this circuit works perfectly.

Even though there is a circuit which is composed of all NPN but it doesn't work properly.

CMOS enter image description here

\$\endgroup\$
  • \$\begingroup\$ Let's consider the first NOR gate circuit step by step. If InputA or InputB euals to Vdd then the output stage will be connected to ground. It is NMOS's behaviour, meanwhile, PMOSes channels will stay closed. \$\endgroup\$ – emre iris May 26 at 8:33
  • \$\begingroup\$ Well you can decorate a room with lights on the floor and a carpet on the ceiling but it would be more complex and less practical but, it could be done. \$\endgroup\$ – Andy aka May 26 at 8:38
  • \$\begingroup\$ @Andyaka yes i understand it this way but i want the technical answer. \$\endgroup\$ – Lileonardo May 26 at 8:50
2
\$\begingroup\$

When using an NMOS for pull-up, for the NMOS to be fully on, you would need a gate voltage that is higher than the supply voltage, see the left schematic:

schematic

simulate this circuit – Schematic created using CircuitLab

Without that higher voltage, shown in the right schematic, you cannot switch the NMOS on fully, the output voltage will be less than the supply voltage.

In the left circuit the NMOS is operated as a switch (which is what you want).

In the right circuit the NMOS is operated as a source follower, the output "follows" the gate voltage with a (somewhat fixed) voltage drop.

For example, for a 5 V supply, the highest output voltage would be 3 V, i.e. you lose about 2 V (the 2 V is just an example, it can be as low as 0.3 V or as high as 5 V depending on the MOSFET you're using). You would need 7 V at the gate to get 5 V at the output. That can be done but is quite complex if you don't have that 7 V available. Using a PMOS is much easier.

It is a similar story for PMOS and pull down (you would need a -2 V supply). The same also applies to using NPNs and PNPs.

| improve this answer | |
\$\endgroup\$
0
\$\begingroup\$

PMOS for pull-up and NMOS for pull-down due to the way there work. That is, due to the fact that NMOS has the source on a lower potential than the gate to be turned on and PMOS has the source on a higher potential than the gate to be turned on:

enter image description here

Source: https://en.wikipedia.org/wiki/MOSFET .

I assume that due to manufacturing problems the focus at the beginning was to manufacture good, reliable (e.g. repeatable Vth) NPN BJT and after that PNP BJT - but for that you need to dig more in the history. Anyway, at the beginning of transitor history, for example opamps were build using only NPN BJT and resistors (see History of Semiconductor Engineering by Bo Lojek. If I remember correctly there is an opamp design done with only NMOS or NPN BJT and resistors done by Bob Widlar). You even have resistor–transistor logic and also transistor–transistor logic. Adding PNP to NPN or PMOS to NMOS (CMOS) gives you more possibilities.

You may change PMOS on NMOS in designs, but a circuit won't work or it working principles will be different. For example in the following opamp design:

enter image description here

Source: https://payhip.com/b/5Srt ("Preview" button in top right corner)

if you change PMOS M7 on NMOS transistor, the second stage no longer amplifies signal but serves as a voltage follower (R1 and C1 are no longer needed for compensation).

| improve this answer | |
\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.