When we deal with a transistor we break it up into two parts, 1 The DC bias. 2 The small signal perturbations. Then we add the currents/voltages from the both the analysis to get the total response. But what is the proof that we can do this procedure? As an example say I've a DC source V and Ac source W. When I apply V at VCB I get x as a response. Then I use the small signal model and find that when I apply a small voltage W I get a response y. The total response is then x+y. However isn't it possible that if i apply V+W together I would end up with a different response?
As an example say I've a DC source V and Ac source W. When I apply V at VCB I get x as a response. Then I use the small signal model and find that when I apply a small voltage W I get a response y. The total response is then x+y. However isn't it possible that if i apply V+W together I would end up with a different response?
Of course if you apply V+W together you end up with a different response (NOT x+y). This is because the circuit is nonlinear so superposition doesn't apply. Separating the dc (bias) and ac (small-signal) response is NOT superposition, though it resembles superposition superficially. What you're actually doing in this case is applying a first-order linear approximation. Do you remember something like this in high-school calculus:
In the image, x is your dc bias voltage and Δx is your ac signal. The true response is f(x+Δx) (nonlinear), but you can approximate the response as f(x) + f'(x)Δx, which is the dc response, f(x), plus the linearized ac response f'(x)Δx. The term f'(x) represents the small-signal gain and is of course dependent on x, the bias point.
Remember that small-signal analysis gives approximate results that are 'close enough' if the excitation signal is kept small enough. Superposition applies only to linear circuits and gives exact results. If you want a proof for why superposition works, that's a whole nother answer.
You cannot prove the linearity of a transistor, because a transistor is non-linear.
However, it's convenient to make linear models to simplify calculations about its operation.
By definition, those linear models are linear.
The way we make a linear model is to take the slope of the curve at a particular point, and use that as the 'linearised' response, around that point. This is a 'small signal' model, explicitly stating the fact that it's only valid for 'small' variations around that point.
Small signal models cease to be useful when we want to use them over parameter ranges where the non-linearity becomes apparent, that is, for large signals.
OK - if I understood you correctly, you want to modify the DC bias voltage as well as the signal voltage - both at the same time? Of course, you can do this if you want.
However, it will be a problem for you to CALCULATE the timely response of a circuit (output voltage) by hand. It will be too involved. But you can try to use a circuit simulator and perform a TRAN analysis in the time domain. In this case, the computer will do the job for you.
However, this procedure has nothing to do with linearity.
[ summary: at end of answer, we predict distortion for "small levels of input" ]
From what I recall, the IP2 'and IP3 of a standard bipolar transistor, tho slightly different numbers, are about -10 dBv.
That means the "Input Intercept" plots, those plots having both
- the 1:1 and 2:1 logarithmic lines for 2nd order distortion
- the 1:1 and 3:1 logarithmic lines for 3rd order distortion
will intercept at about -10 dBv.
Thus, for either 2nd or 3rd order, the produced_distortion has the same voltage as the input signal, at input of -10dBv.
What is we dropped the input level by 50dB?
The 2nd order distortion would drop by 50dB, as predicted by 1:1 and 2:1 lines.
The 3rd order distortion would drop by (2 * 50dB), as predicted by 1:1 and 3:1 lines.