I am designing a very small signal conditioning daughterboard with the intent of mounting it directly underneath a cylindrical piezoelectric force device/"sensor" to rectify and filter the differential voltage generated across the two pins.

The piezo device is about 60mm in diameter, and the PCB will be near the same with two through-holes for attaching the piezo device.

Thus, from the "top down" view, the footprint of the PCB will not add any new area, rather be directly under the transducer.

Having selected EMF hardened components as well as other common practices like copper pour, do you think this physical design has any glaring issues from a signal standpoint?

The transducer generates a fairly large signal at around 1.5Vpp. my main concern is some sort of capacitance issues being so close to the transducer.

  • \$\begingroup\$ I assume you have overvoltage protection in case your transducer generates a high voltage spike? \$\endgroup\$ Commented Sep 17, 2020 at 11:01
  • \$\begingroup\$ Sure, I don't think that assumption really has much to do with the question though. The inquiry is more about any signal issues resulting from their relative positions. \$\endgroup\$
    – Ben Longo
    Commented Sep 18, 2020 at 22:15
  • \$\begingroup\$ @Matt did you end up creating a design like this? \$\endgroup\$
    – Ben Longo
    Commented Sep 18, 2020 at 22:17
  • 1
    \$\begingroup\$ how anybody should tell without 3D drawings, PCB Layout and such? What frequencies the signal will have (force sensor indicates some 10th kHz at worst)... \$\endgroup\$
    – schnedan
    Commented Sep 20, 2020 at 9:03
  • \$\begingroup\$ fwiw I found a couple similar designs online pyroballpcbs.com/product/pp-singledisk-adapter-pcb precisionpiezo.co.uk/product-page/precision-piezo-orion-kit \$\endgroup\$
    – Ben Longo
    Commented Sep 29, 2020 at 21:18


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