# Tri State Buffer and Boolean Algebra

The basic operators of the boolean algebra are AND, OR, NOT. The modern digital circuits are based on this mathematical concept (Shannon's thesis, 1938). I am wondering whether the Tri-State Buffer can be build (represented logically) with only these three operators (gates)?

Boolean logic (propositional calculus) is an idealized, mathematical formal system which has exactly two variable values, True and False. The Boolean operators { AND, OR, NOT } are sufficient to synthesize any Boolean expression, and even the set of { NAND } by itself is also sufficient (since NOT X = X NAND X, A AND B = NOT (A NAND B), A OR B = (NOT A) NAND (NOT B)). But there is a missing piece if you're trying to model a tri-state system. There is no set of Boolean operators that can produce a value that is simultaneously not-True and not-False. A single Boolean variable must be either True or False, there is no such thing as a Boolean tri-state value.

In practical digital logic circuits, we map the Boolean True and False values to a range of voltages, such as a "logic low" (V < 0.7V) for Boolean False and "logic high" (V > 2.4V) for Boolean True. There is a range of voltages that has no defined logic value; this is an essential part of the "noise immunity" which is the primary advantage of digital logic.

What makes an output an output is its relatively low source impedance. Inputs are expected to draw negligible input current, so their input impedance needs to be fairly high (>6000 ohms). Outputs need to be able to drive the parasitic capacitance of wiring and PCB routes, so an output needs to be fairly low impedance (<100 ohms). But if the transistors that drive the output are "switched off", then the output pin is no longer driven by the output: that's what is meant by "high-impedance" or "tri-state".

At a system level, what happens when a device makes its output high-impedance (or tri-state), is not determined by the tri-state device but rather determined by other parts of the system. Usually there is a requirement for some passive termination to pull the signal to some predetermined level, like VDD/2, otherwise the voltage could drift into the logic low or logic high range. Typically the use case for tri-state logic is to allow more than one device to share the output driving capability, though not all can drive the output at the same time. This is closely related to open-drain outputs or open-collector outputs, which can only pull the signal to logic low but require an external passive device to make the logic high default signal when no driver is active.

There is a way to model tri-state output behavior, but it requires using two Boolean variables instead of one: one variable is used to enable the output, and when not-enabled, then the value of the pin is tri-state. This is not a Boolean value, it's a practical digital logic state represented by the combination of two Boolean variables.

The missing piece is called a transmission gate; the symbol is usually drawn like two intersecting triangles or a six-pointed star. See this answer: https://electronics.stackexchange.com/a/158244/35022 and What is this schematic symbol with intersecting triangles? This is not a Boolean operator, but it is one of the basic building blocks of digital logic, and it is controlled by a logical enable input. So it is possible to synthesize Boolean equations for output-value and output-enable, and then those two Boolean values control the transmission gate. If you wanted to synthesize a tri-state logic function in an FPGA, you could describe it using verilog, which supports 1/0/z wire values, and a typical FPGA would have low-level output pin primitives that have an output-enable.

Three state buffering is created to save costs when only one signal at a time is allowed to set the state for an input. It is logically a technical multiplexing method. Multiplexers can well be constructed by using gates (and, or, not). That's complex but surely works.

ADD: If you can accept 1 and 0 have the same meaning as in Shannon's original switching algebra the case is trivial. There 0 and 1 present "is there a connection or not" . Presenting voltage levels as logic states wasn't his starting point. His text starts by presenting switches as objects that can have state 0 or 1. Three state buffers can be considered to be his controlled switches (=relays) which in their conductive state pass what's available.

So, stop wondering; the answer is YES.

If you still wonder how we could make 3 state buffering only by connecting wires from outputs of basic logic gates to inputs of basic logic gates stop it, too . The solution doesn't exist because no input to any gate doesn't insert the 3rd state as you can see in the truth tables.

• " So, stop wondering; the answer is YES." - How? May 26 '20 at 23:02
• there's a finite state machine which resolves the write requests and answers to them by ack and setting the right selection number to the select inputs of all multiplexers. The number = the id of accepted talker. Every device has a N to 1 multiplexer in every bus line (lines for data and address) where N is the number of devices which can have a right to speak. For every conceptual bus line terminal of a device there's an input for a multiplexer output and an output which is connected to an input in every multiplexer May 26 '20 at 23:38
• But the output of any multiplexer is binary (1 or 0). This is not true for the three state buffering where the output can be Hi-Z. This latter is not defined in the boolean algebra. May 27 '20 at 0:35
• I didn't claim anything of the number of states in 3 state outputs. I wrote how the data routing to devices can be defined as basic gate operations. Building it physically with 3-state outputs is a lot cheaper method than using multiplexers to realize the logically same functionality. May 27 '20 at 8:22