I am trying to layout DDR3 128MB chip and a Spartan-6 FPGA. DDR signal pins located on specific memory controller pins and could not be swapped. I've never done DDR routing and went with SP605 Xilinx board schematic as a reference to minimise points of human error. I've search for fair amount of literature but i absolutely have no experience on DDR memory and kind-of scared. So I've split DDR3 memory signals into this groups(net classes).

net class   L min   L max   vias/trace
sdram_ud    19.905  19.931  2
sdram_ld    20.244  20.293  0
sdram_clk   19.102  19.106  2
sdram_addr  31.775  32.77   0..2
sdram_ctl   31.736  32.082  0..2

sdram_ud (pink):
    udqsn, udqsp
sdram_ud (blue):
    ldqsn, ldqsp
sdram_addr (orange):
    we, cas, ras
sdram_clk (yellow):
    ckp, ckn
sdram_ctl (green):
    cs, clke, rst, odt

L1 L3 L6

Ground and power planes are omitted on the screenshots.

All classes were routed in order they listed. sdram_ld and sdram_ud routed on different layers. All of the members of sdram_ctl class pulled to ground via 4k7 Ohm. All of the members of sdram_addr class terminated to vtt via 50 Ohm resistor pack on the bottom layer. I've put as many decoupling caps as i could: 0603/0402 ceramic 0.1uf + one big 4u7f polymer.

DDR3 layed out on 6-layer board with this stackup:
L1 signal/power
L2 gnd
L3 signal
L4 gnd
L5 power
L6 signal/power

Signal track width is 0.125mm. With my standard manufacturer's stackup it is around 70 Ohm impedance. Is it enough or I need to quote for custom stackup?

DDR3 signals located on L1 and L3. Termination, decoupling, vref and vtt located on L6. There is 1v5 island on L5 under Memory and FPGA part.

I've tried to follow S/3S rule, but not really worked out for me, I guess. I've layed out and tuned everything by hand. Addr class still looks like mess to me, but this is my best run so far. DQ signals are swapped within DQ[15..8] and DQ[7..0]. sdram_ctl tuned to match sdram_addr. sdram_ud is not tuned to match sdram_ld just so happened.

My questions are: Is this design will work at lowest possible speed at least? Did i correctly split DDR3 signals into classes? Is such difference betwin classes track length ok? As far as i understand DDR calibration is the process of compensation delays of net classes relative to the clock (ckp, ckn). Is it ok to have some address lines routed on one side, and others on the other? Do i have enough track clearance?

Also, looks like Altium does not account for vias length, so length tolerances might be +-1.5mm more for addr class.

UPD: DDR3 Chip is MT41J64M16LA in 96ball FBGA (0.8mm pitch) FPGA Chip is XC6SLX45T in 484ball BGA (1mm pitch)

UPD2: Dark red traces at L6 is vref net.

  • \$\begingroup\$ Have you accounted for the package delays at both ends? \$\endgroup\$ Commented May 27, 2020 at 18:48
  • \$\begingroup\$ @pericynthion No, I am assuming that DDR package is ideal. As for FPGA side i think it is more of synthesis/implementation problem. \$\endgroup\$ Commented May 27, 2020 at 19:06
  • \$\begingroup\$ @pericynthion Furthermore there is Xilinx reply forums.xilinx.com/t5/Processor-System-Design-and-AXI/… \$\endgroup\$ Commented May 27, 2020 at 19:10
  • \$\begingroup\$ Ok, makes sense! \$\endgroup\$ Commented May 27, 2020 at 19:15
  • \$\begingroup\$ Did your solution work at the end? Which PCB design software did you use? \$\endgroup\$
    – gyuunyuu
    Commented Sep 10, 2020 at 22:53

3 Answers 3


So, i've finally assembled board with this design and DDR3 portion ended up working @ 333MHz. Although now i think traces is way too close to each other. W/3W rule must be kept.

EDIT: Keep in mind that this design have very short(relatively) clock line. Some calibration algorithms on some systems may not work.

EDIT: Yeah, my trace impedance is ~60Ohms. And there is no VTT/Vref ic on those images of mine OP.

  • 1
    \$\begingroup\$ Thanks for following up! Did it not work at faster speeds? What was the symptom? \$\endgroup\$ Commented Sep 10, 2020 at 7:31
  • \$\begingroup\$ How long did it take to complete this PCB layout and reach the stage of hardware testing? Which PCB design software did you use? \$\endgroup\$
    – gyuunyuu
    Commented Sep 10, 2020 at 22:54
  • 1
    \$\begingroup\$ @pericynthion I've used Xilinx's MIG to generate MCB core. I've just plonk maximum speed value it offered. \$\endgroup\$ Commented Sep 11, 2020 at 9:09
  • 1
    \$\begingroup\$ Did you carry out simulation of the DDR3 traces and other high speed traces in Altium designer? Have you used Hyperlynx? When you say doing it in freetime, how much is that per day or per week? \$\endgroup\$
    – gyuunyuu
    Commented Sep 11, 2020 at 20:53
  • 4
    \$\begingroup\$ @Quantum0xE7 Nah, I did not simulate anything. But I've googled up a ton of DDR3/DDR2 boards and design screenshots. And I saw that some designs routed so hit or miss. As i have SRAM in the design i had backup, so I just yolo it. Very much time went to actually understand what and how i want things done. Choosing parts, reading docs, checking other designs, watching tutorials etc. Sometimes I've spend 1 whole day per week and sometimes I've spend 3/4 hours per day for whole week. I would roundup to 1 hour a day or less. Some design stages fun, and others boring, depends on that. \$\endgroup\$ Commented Sep 12, 2020 at 5:42

Your clk, addr, and ctl class should actually be just one class. Typically named CA. Your clock is indeed short. It should match CA.

Some tips to make your life easier in the future:

  • Route ALL signals in a class on the same layer. That way all signals in a class will have the exact same number and type of vias, and the same dielectric constant and propagation velocity. So that it all cancels out automatically.

  • The 50 ohm termination resistors can in most cases be omitted in point-to-point designs like this where CA only feeds a single SDRAM. Saves tons of power, simplifies layout, and removes the need for a VTT regulator. But you may want to keep the clock termination resistor.

  • Package delays on the CPU/FPGA side must be compensated for on high performance designs. Package delay is essentially the varying length bond wires from the silicon to the BGA ball. It has nothing to do with synthesis/implementation.

But at 333MHz you have quite a bit of margins for mistakes.

  • \$\begingroup\$ how does one ensure that the via has 50 ohm impedance as well? \$\endgroup\$
    – quantum231
    Commented Apr 25, 2023 at 9:08
  • \$\begingroup\$ Impedance controlled vias is not neccessary for 333MHz DDR3 \$\endgroup\$ Commented May 7, 2023 at 19:53
  • \$\begingroup\$ ok, what about 800 MHz then? How do I know if impedance controlled via is required or not without simulation? \$\endgroup\$
    – quantum231
    Commented May 7, 2023 at 21:34
  • \$\begingroup\$ Impedance controlled vias are not really used for DDR memory buses at all. Just make sure there are a couple of GND vias in the vicinity of your signal vias, and you will be alright. The length matching routing requirements of DDR busses are much more important than via impedances. \$\endgroup\$ Commented May 15, 2023 at 11:21
  • \$\begingroup\$ See the basic idea is like this, we go through a huge huge huge amount of effort to make sure that the signal path has uniform impedance. We use a specific stack up for the PCB. We set the track width based on the distance from ground plane and copper weight. We ensure that the reference plane has no breaks. We make sure that the dielectric material mesh is uniform so the dielectric constant does not change as the signal is travelling in the field created between the PCB track and reference plane. Now, a via is a impedance discontinuity in the signal path. Why don't we treat it seriously? \$\endgroup\$
    – quantum231
    Commented May 15, 2023 at 13:16

As you mentioned the master clock is very short. I guess the red trace is for Vref voltage. You must connect it with a wider trace or polygon. You may try L4 as a signal in the stack up. L3-L4 must be thicker core material than the other core or prepregs. They should not influence each other.


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