# Understanding balancing resistor in bipolar op amp

I just can't understand compensation resistor in bipolar op amp. And reading other answers in Reason behind choosing the compensating resistor for input bias current in op amps or How does the compensating resistor act in op amp haven't cleared my confusion.

1. Is the "input bias current" the current generated from external power source or some unwanted current resulted from within the op amp circuitry when the op amp is powered? In my learning of BJT, input bias means setting the Q-Point by coupling a DC voltage to the base of a transistor. So my assumption of input bias in op amp is the DC part of the input signal, but elsewhere they state the input bias is due to transistor mismatches within the op amp circuitry - hence the bias current is an "unwanted" current induced from within the op amp. But if it's an unwanted current needing to be gotten rid of, it can't possibly be called an input bias - it's neither a meaningful input for any operation nor a bias to set a system up to center an amplified signal. Neither of my interpretations is correct. What exactly is input bias current?

2. In the diagram, when there exists a potential difference between $$\ V_- \$$ and $$\ V_+ \$$ then an $$\ I_{OUT} \$$ will be generated to zero out the input potential through $$\ R_2 \$$ and $$\ R_1 \$$ voltage divider. $$\ V_+ \$$ is grounded to 0V regardless of the size of $$\ R_3 \$$. And seeing from the op amp circuitry, the inverting input's emitter sees $$\ {R_2 \parallel R_1} \over \beta \$$, and the non-inverting input's collector sees $$\ {R_3} \over \beta \$$. So the op amp behind the inputs sees a total resistance of $$\ {R_2 \parallel R_1 + R_3} \over \beta \$$. Adding the compensating $$\ R_3 \$$ only adds to the resistance seeing from the op amp, how is it balancing or compensating anything?

• V+ is not connected to the ground, it would be true if there would not be any current flowing through there. V+ is connected to R3*I_bias volts of potential. Commented May 28, 2020 at 1:13
• @muyustan you're right let me strike that out. But question somewhat remains or if I term it differently: a current in collector-emitter side generates or pulls $I_c \over \beta$ current into the base after the voltage drop over $R_3$. So the size of $R_3$ only changes its own voltage drop but current into + (or base of a BJT) remains a value dictated by its collector current inside the op amp. Wow this is confusing - a collector current induces a base current??
– KMC
Commented May 28, 2020 at 1:59
• – G36
Commented May 28, 2020 at 3:30
• And with the compensating resistor i.sstatic.net/FbltQ.jpg
– G36
Commented May 28, 2020 at 3:37
• It's simply the base current of the input BJTs.
– user16324
Commented May 28, 2020 at 12:13

Is the "input bias current" the current generated from external power source or some unwanted current resulted from within the op amp circuitry when the op amp is powered?

The op-amp bias current is that small current that is needed by the op-amp's inputs to properly operate the device. This isn't always equal for both inputs and pretty much all data sheets refer to the difference in input bias currents as input offset current. That offset is unknown (without measurement) and may also change over time hence, using resistors to try and cancel offset current is not effective.

So you might have an input bias current specification of 100 nA and an input offset current specified as 10 nA. This might mean the true bias currents into the inputs are: -

• +110 nA for one input
• +90 nA for the other input

Equal value resistances in both input circuits will cancel the bias current but the offset current is still an unknown and cannot be easily reduced because we don't know what it is.

So the effect of input resistors causes both inputs to be slightly raised or lowered by the same amount when there is exactly equal bias currents and, this means that there is no extra offset voltage at the inputs that leads to the same error as what is called input offset voltage (another parameter in the data sheet for all op-amps).

Two causes of output error, known as output offset voltage are:

1) Input offset voltage. 2) Input bias currents.

(Mismatch of the input stage degeneration resistors also contributes to output offset voltage.)

Input offset voltage is caused by VBE mismatch in the two input transistors due to manufacturing tolerances.

Input bias currents are currents flowing into (NPN input transistors) or out of (PNP input transistors) the op amp’s inputs. The input transistors must have these base currents in order to enable collector currents to flow in the input stage.

To understand these two causes of output offset it is best to consider each separately as their individual effects add together to cause the total output offset voltage. Under certain conditions the two effects can partially cancel each other out.

So, as your question is about the output errors caused by the input bias currents, let’s consider the ideal situation where the input offset voltage VOS is zero and the output offset voltage is caused solely by the input bias currents.

Let’s consider the situation where the input to the circuit VIN = 0V.

Because the input transistors’ collector currents are fixed (by the input stage current source) it means that their base currents are also a constant current. In reality these base currents will have a different value to each other due to hFE manufacturing mismatch in the two input transistors.

Let’s assume the ideal case where the two input transistors’ hFEs are perfectly matched and so the bias currents are equal.

Let’s also start without R3 and so the non-inverting input is connected directly to 0V. Now, because we are assuming VOS = VIN = 0V, then the inverting input is also at 0V and no current flows in R1 (both ends of R1 at 0V).

The non-inverting input’s bias current flows directly to ground and therefore has no effect on the output. However, the inverting input’s bias current must flow through R2 and therefore causes a voltage offset at the output equal to –IBIAS * R2.

Now if we insert R3 into the circuit, IBIAS flowing through R3 causes a voltage drop across R3 which jacks up both inputs by the same voltage. This means that there is now a current flowing in R1 and therefore less current than there was flowing through R2. (Remember IBIAS is fixed).

It turns out that if R3 is made equal to R1//R2 then the inputs are jacked up by just the right amount to remove the output offset voltage and bring the output to 0V. This cancellation only works perfectly in the ideal case where the base currents are equal.