0
\$\begingroup\$

I want to make a PLL which will lock to the subcarrier of a composite video signal during colourburst. The colourburst is present for about 2.25uS of each scanline which is 64uS long. So during that 2.25uS I need the phase detector to apply a control voltage to the VCXO. The rest of the time, the VCXO needs to coast. The control voltage during this period should remain at what it was during the last colourburst interval.

During colourburst, the voltage at Gate will be low and the phase detector should be connected to the loop filter (R2 / C1). Other times the gate voltage will be high, the circuit between the phase detector and loop filter will be open, and C1 will maintain its charge.

Can I use 2 P-channel mosfets back to back in this way to gate the output of the phase detector? Is there a better way to achieve this?

schematic

simulate this circuit – Schematic created using CircuitLab

\$\endgroup\$
3
  • \$\begingroup\$ What you are looking for is called a "sample and hold" circuit. \$\endgroup\$ May 28 '20 at 11:33
  • \$\begingroup\$ It would be better to use a JFET in this application. \$\endgroup\$
    – Dave Tweed
    May 28 '20 at 11:40
  • \$\begingroup\$ Or a transmission gate. \$\endgroup\$
    – Andy aka
    May 28 '20 at 13:02

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Browse other questions tagged or ask your own question.