# Design of class AB output stage

I'm trying to design an audio amplifier output stage to drive a speaker load. I'd like to start with the design of this stage in order to calculate the input impedance to the output stage so that I can proceed to designing a buffer stage with an appropriate output impedance and a gain stage before that.

My speaker impedence is 8 Ω and I'd like to deliver a minimum of 1 W to the load and keep total harmonic distortion below 1%. One possible class AB output stage configuration is given below. I looked at a few different configurations, but this one is nice in that it doesn't require a constant current source for the biasing which makes it simpler:

I first began by calculating the peak voltage over the load:

$$\Vp = \sqrt{2R_LP_l} = \sqrt{2(8)(1)}=4\ \textrm{V}\$$

From this I calculated the maximum output current through the load to be 2 mA using Ohm's law, assuming R3 and R4 to be 0 for the time being (I can add these values back if I notice any thermal runaway effects later).

Since the voltage gain of this output stage is approximately unity, the output current which I calculated as 2 mA is related to the input current through the current gain given by:

$$A_i = \frac{i_o}{i_i}=\frac{(1+\beta)R}{2R_L}$$

The textbook I'm using has made the assumption that all of the transistors, NPN and PNP, are perfectly matched when they derive the current gain. This is obviously not true in reality. The 2N3904 NPN transistors and the 2N3906 transistors I'd like to use have very different current gains.

How can I solve for my bias resistors R1 and R2 such that I keep the total harmonic distortion low, while still supplying the output current that satisfies the power requirement? What is a more practical/real-world design approach for designing this output stage? I find that the theory in the textbook is often quite useless when it comes to designing real applications.

• What do R1 and R2 do? They provide bias current for Q1 and Q2. What happens if for example the bias current of Q1 is too low? Then Q1 will be "out of current" under certain conditions. What are the conditions that Q1 + R1 need to source/sink the lowest / highest current? Well, what Base current will Q3 need? Determine the maximum collector current of Q3, divide that by the lowest $\beta$ you expect, take margin on that (like a factor 2), that will be the current that Q1 and R1 must be able to push/pull into Q3. Commented May 28, 2020 at 14:19
• This circuit arrangement is tempting. A problem you haven't addressed is temperature tracking...if you can keep all transistors at the same temperature it can work very nicely. But Q3,Q4 tend to run hot with large signals while Q1,Q2 consume more-constant power. Thermal design gets a bit complicated. Commented May 28, 2020 at 14:44
• Here you find what you want uweb.engr.arizona.edu/~brew/ece304spr07/Pdf/…
– G36
Commented May 28, 2020 at 16:03
• Are you sure about that value for the current? Commented May 28, 2020 at 18:17