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I want to design this circuit using the Verilog HDL. However, I can't make a feedback part well.

Here is my code.

`define TAP7 7'b1000001

`define TAPS `TAP7

module TEST_LFSR_2(Clock,Reset,Y);
    parameter Width=7; /*bit parameter*/

    input Clock,Reset;
    output [Width-1:0]Y;

    wire [Width-1:0]Taps;
    integer N;
    
    reg [1:0] semiFeedback;
    reg Bits0_Nminus1_Zero,Feedback;
    reg [Width-1:0]LFSR_Reg,Next_LFSR_Reg;

assign  Taps [Width-1:0]=`TAPS;

always@ (negedge Reset or posedge Clock)
    begin : LFSR_Register
        if(!Reset)
            LFSR_Reg=0;
        else
            LFSR_Reg = Next_LFSR_Reg;
    end

always@(LFSR_Reg)
    begin:LFSR_Feedback

        Bits0_Nminus1_Zero=~| LFSR_Reg[Width-2:0];
        
    

    for(N=Width-1;N>=1;N=N-1)
                Next_LFSR_Reg[N]=LFSR_Reg[N-1];
                
                if (Taps[N]==1)
                    Feedback=^LFSR_Reg[N];
                    
                Next_LFSR_Reg[0]=Feedback^Bits0_Nminus1_Zero;
    end
        
    
    assign Y=LFSR_Reg; 
endmodule

I want to make an N-bit LFSR. After checking the TAPS's bit that has 1, I want to XOR each bit that has 1. However, I don't know how to do it.

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1 Answer 1

2
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I'm not sure where you're going with all of that Verilog code, but your diagram basically boils down to the following statements:

wire [7:0] mask = 8'b01110001;
reg [7:0] LFSR_Reg;

always @(posedge Clock)
  LFSR_Reg <= Reset ? 8'b10000000 : {^(LFSR_Reg & mask), LFSR_Reg[7:1]};

Use the power of the language to avoid unnecessary work!

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  • \$\begingroup\$ Except you should use non-blocking assignment, <=, inside the sequential always block. \$\endgroup\$
    – Matt
    May 29, 2020 at 4:35
  • \$\begingroup\$ @Matt: Technically, since it's a single statement and not a block, the type of assignment makes no difference at all. But as a teaching example, you're right -- I should establish the correct habit. \$\endgroup\$
    – Dave Tweed
    May 29, 2020 at 10:44

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