I'm working on implementing the privileged RISC V ISA, which can be found here.
I'm looking at the bottom of page 20, and the interrupt conditions are stated very confusingly:
Global interrupt-enable bits, MIE, SIE, and UIE, are provided for each privilege mode. These bits are primarily used to guarantee atomicity with respect to interrupt handlers in the current privilege mode.
The global x IE bits are located in the low-order bits of mstatus, allowing them to be atomically set or cleared with a single CSR instruction.
When a hart is executing in privilege mode x, interrupts are globally enabled when x IE=1 and globally disabled when x IE=0. Interrupts for lower-privilege modes, wx, are always globally enabled regardless of the setting of the higherprivilege mode’s global y IE bit. Higher-privilege-level code can use separate per-interrupt enable bits to disable selected higher-privilege-mode interrupts before ceding control to a lower-privilege mode.
With this description, I have made the following truth table which determines whether or not a certain interrupt will be execute based upon the MIE, SIE, and UIE bits, and the current privilege mode. This is confusing because it seems like while execution as a user, the supervisor won't take interrupts of a higher privilege level... Is that correct?
is this truth table correct?